Commit cebc13de authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Whitelist COMMON_SLICE_CHICKEN3 for UMD access



A recommended tuning setting for both gen12 and Xe_HP platforms requires
that we grant userspace r/w access to the COMMON_SLICE_CHICKEN3
register.

Bspec: 73993, 73994, 31870, 68331
Cc: Dongwon Kim <dongwon.kim@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230224002300.3578985-1-matthew.d.roper@intel.com
parent 7416cbbc
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+23 −1
Original line number Diff line number Diff line
@@ -2227,6 +2227,10 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)

		/* Wa_1806527549:tgl */
		whitelist_reg(w, HIZ_CHICKEN);

		/* Required by recommended tuning setting (not a workaround) */
		whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3);

		break;
	default:
		break;
@@ -2274,6 +2278,9 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine)
					  RING_FORCE_TO_NONPRIV_ACCESS_RD |
					  RING_FORCE_TO_NONPRIV_RANGE_4);

		/* Required by recommended tuning setting (not a workaround) */
		whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);

		break;
	case COMPUTE_CLASS:
		/* Wa_16011157294:dg2_g10 */
@@ -2311,6 +2318,21 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
	blacklist_trtt(engine);
}

static void mtl_whitelist_build(struct intel_engine_cs *engine)
{
	struct i915_wa_list *w = &engine->whitelist;

	switch (engine->class) {
	case RENDER_CLASS:
		/* Required by recommended tuning setting (not a workaround) */
		whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);

		break;
	default:
		break;
	}
}

void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
	struct drm_i915_private *i915 = engine->i915;
@@ -2319,7 +2341,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
	wa_init_start(w, engine->gt, "whitelist", engine->name);

	if (IS_METEORLAKE(i915))
		; /* noop; none at this time */
		mtl_whitelist_build(engine);
	else if (IS_PONTEVECCHIO(i915))
		pvc_whitelist_build(engine);
	else if (IS_DG2(i915))