Commit cf5f06c8 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-renesas', 'clk-cleanup', 'clk-hisilicon', 'clk-mediatek'... 

Merge branches 'clk-renesas', 'clk-cleanup', 'clk-hisilicon', 'clk-mediatek' and 'clk-bulk' into clk-next

 - Add a devm_clk_bulk_get_all_enable() API to get and enable all clks
   for a device
 - Fix some static checker errors in the hisilicon clk driver

* clk-renesas: (25 commits)
  clk: renesas: r8a779h0: Add RPC-IF clock
  clk: renesas: r8a779h0: Add SYS-DMAC clocks
  clk: renesas: r8a779h0: Add SDHI clock
  clk: renesas: r8a779h0: Add EtherAVB clocks
  clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
  clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux
  clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
  clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
  clk: renesas: r8a779h0: Add I2C clocks
  clk: renesas: r8a779h0: Add watchdog clock
  clk: renesas: r8a779h0: Add PFC/GPIO clocks
  clk: renesas: r8a779g0: Fix PCIe clock name
  clk: renesas: cpg-mssr: Add support for R-Car V4M
  clk: renesas: rcar-gen4: Add support for FRQCRC1
  clk: renesas: r9a07g043: Add clock and reset entries for CRU
  clk: renesas: r9a08g045: Add clock and reset support for watchdog
  dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
  dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support
  dt-bindings: power: Add r8a779h0 SYSC power domain definitions
  dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support
  ...

* clk-cleanup:
  clk: zynq: Prevent null pointer dereference caused by kmalloc failure
  clk: fractional-divider: Use bit operations consistently
  clk: fractional-divider: Move mask calculations out of lock
  clk: ti: dpll3xxx: use correct function names in kernel-doc
  clk: clocking-wizard: Remove redundant initialization of pointer div_addr
  clk: keystone: sci-clk: match func name comment to actual
  clk: cdce925: Remove redundant assignment to variable 'rate'
  MAINTAINERS: drop Sekhar Nori

* clk-hisilicon:
  clk: hisilicon: Use devm_kcalloc() instead of devm_kzalloc()
  clk: hisilicon: hi3559a: Fix an erroneous devm_kfree()
  clk: hisilicon: hi3519: Release the correct number of gates in hi3519_clk_unregister()

* clk-mediatek:
  clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe()
  clk: mediatek: add infracfg reset controller for mt7988
  dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs
  dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock
  dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock
  dt-bindings: clock: mediatek: convert hifsys to the json-schema clock
  clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
  clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF
  clk: mediatek: mt7622-apmixedsys: Fix an error handling path in clk_mt8135_apmixed_probe()
  clk: mediatek: mt8135: Fix an error handling path in clk_mt8135_apmixed_probe()

* clk-bulk:
  clk: Provide managed helper to get and enable bulk clocks
parents 9bd5726f 7938e9ce 252c31a9 f40056a5 265b07df

CREDITS

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@@ -2942,6 +2942,11 @@ S: 2364 Old Trail Drive 
S: Reston, Virginia 20191

S: USA



N: Sekhar Nori

E: nori.sekhar@gmail.com

D: Maintainer of Texas Instruments DaVinci machine support, contributor

D: to device drivers relevant to that SoC family.



N: Fredrik Noring

E: noring@nocrew.org

W: http://www.lysator.liu.se/~noring/

Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt

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Mediatek hifsys controller

============================



The Mediatek hifsys controller provides various clocks and reset

outputs to the system.



Required Properties:



- compatible: Should be:

	- "mediatek,mt2701-hifsys", "syscon"

	- "mediatek,mt7622-hifsys", "syscon"

	- "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"

- #clock-cells: Must be 1



The hifsys controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.



Example:



hifsys: clock-controller@1a000000 {

	compatible = "mediatek,mt2701-hifsys", "syscon";

	reg = <0 0x1a000000 0 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt

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MediaTek PCIESYS controller

============================



The MediaTek PCIESYS controller provides various clocks to the system.



Required Properties:



- compatible: Should be:

	- "mediatek,mt7622-pciesys", "syscon"

	- "mediatek,mt7629-pciesys", "syscon"

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The PCIESYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.



Example:



pciesys: pciesys@1a100800 {

	compatible = "mediatek,mt7622-pciesys", "syscon";

	reg = <0 0x1a100800 0 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt

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MediaTek SSUSBSYS controller

============================



The MediaTek SSUSBSYS controller provides various clocks to the system.



Required Properties:



- compatible: Should be:

	- "mediatek,mt7622-ssusbsys", "syscon"

	- "mediatek,mt7629-ssusbsys", "syscon"

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The SSUSBSYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.



Example:



ssusbsys: ssusbsys@1a000000 {

	compatible = "mediatek,mt7622-ssusbsys", "syscon";

	reg = <0 0x1a000000 0 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek HIFSYS clock and reset controller



description:

  The MediaTek HIFSYS controller provides various clocks and reset outputs to

  the system.



maintainers:

  - Matthias Brugger <matthias.bgg@gmail.com>



properties:

  compatible:

    oneOf:

      - enum:

          - mediatek,mt2701-hifsys

          - mediatek,mt7622-hifsys

      - items:

          - enum:

              - mediatek,mt7623-hifsys

          - const: mediatek,mt2701-hifsys



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1

    description: The available clocks are defined in dt-bindings/clock/mt*-clk.h



  "#reset-cells":

    const: 1



required:

  - reg

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    clock-controller@1a000000 {

        compatible = "mediatek,mt2701-hifsys";

        reg = <0x1a000000 0x1000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

    };