Commit d32fb60f authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo
Browse files

ARM: dts: imx7[d]-mba7: Move ethernet PHY reset into PHY node 



Split pinctrl as well. 'reset-deassert-us' is added with a small safe
margin.

Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e67e40cf

arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi

+10 −3
Original line number Diff line number Diff line
@@ -214,8 +214,6 @@ &fec1 { 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet1>;

	phy-mode = "rgmii-id";

	phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;

	phy-reset-duration = <1>;

	phy-supply = <&reg_fec1_pwdn>;

	phy-handle = <&ethphy1_0>;

	fsl,magic-packet;
@@ -228,10 +226,15 @@ mdio { 
		ethphy1_0: ethernet-phy@0 {

			compatible = "ethernet-phy-ieee802.3-c22";

			reg = <0>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_enet1_phy>;

			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;

			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;

			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;

			reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;

			reset-assert-us = <1000>;

			reset-deassert-us = <500>;

		};

	};

};
@@ -366,7 +369,11 @@ pinctrl_enet1: enet1grp { 
			<MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1		0x79>,

			<MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2		0x79>,

			<MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3		0x79>,

			<MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x79>,

			<MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x79>;

	};



	pinctrl_enet1_phy: enet1phygrp {

		fsl,pins =

			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */

			<MX7D_PAD_ENET1_COL__GPIO7_IO15				0x40000070>,

			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */

arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts

+10 −3
Original line number Diff line number Diff line
@@ -21,8 +21,6 @@ &fec2 { 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet2>;

	phy-mode = "rgmii-id";

	phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;

	phy-reset-duration = <1>;

	phy-supply = <&reg_fec2_pwdn>;

	phy-handle = <&ethphy2_0>;

	fsl,magic-packet;
@@ -35,10 +33,15 @@ mdio { 
		ethphy2_0: ethernet-phy@0 {

			compatible = "ethernet-phy-ieee802.3-c22";

			reg = <0>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_enet2_phy>;

			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;

			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;

			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;

			reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;

			reset-assert-us = <1000>;

			reset-deassert-us = <500>;

		};

	};

};
@@ -62,7 +65,11 @@ pinctrl_enet2: enet2grp { 
			<MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x79>,

			<MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x79>,

			<MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x79>,

			<MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL	0x79>,

			<MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL	0x79>;

	};



	pinctrl_enet2_phy: enet2phygrp {

		fsl,pins =

			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */

			<MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x40000070>,

			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */