Unverified Commit d4b500cc authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "riscv: 64-bit NOMMU fixes and enhancements" 

Samuel Holland <samuel.holland@sifive.com> says:

This series aims to improve support for NOMMU, specifically by making it
easier to test NOMMU kernels in QEMU and on various widely-available
hardware (errata permitting). After all, everything supports Svbare...

After applying this series, a NOMMU kernel based on defconfig (changing
only the three options below*) boots to userspace on QEMU when passed as
-kernel.

  # CONFIG_RISCV_M_MODE is not set
  # CONFIG_MMU is not set
  CONFIG_NONPORTABLE=y

*if you are using LLD, you must also disable BPF_SYSCALL and KALLSYMS,
because LLD bails on out-of-range references to undefined weak symbols.

* b4-shazam-merge:
  riscv: Allow NOMMU kernels to run in S-mode
  riscv: Remove MMU dependency from Zbb and Zicboz
  riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
  riscv: Fix TASK_SIZE on 64-bit NOMMU

Link: https://lore.kernel.org/r/20240227003630.3634533-1-samuel.holland@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 70a57b24 f862bbf4

arch/riscv/Kconfig

+10 −7
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ config RISCV 
	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE

	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU

	select BUILDTIME_TABLE_SORT if MMU

	select CLINT_TIMER if !MMU

	select CLINT_TIMER if RISCV_M_MODE

	select CLONE_BACKWARDS

	select COMMON_CLK

	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
@@ -230,8 +230,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX 


# set if we run in machine mode, cleared if we run in supervisor mode

config RISCV_M_MODE

	bool

	default !MMU

	bool "Build a kernel that runs in machine mode"

	depends on !MMU

	default y

	help

	  Select this option if you want to run the kernel in M-mode,

	  without the assistance of any other firmware.



# set if we are running in S-mode and can use SBI calls

config RISCV_SBI
@@ -248,8 +252,9 @@ config MMU 


config PAGE_OFFSET

	hex

	default 0xC0000000 if 32BIT && MMU

	default 0x80000000 if !MMU

	default 0x80000000 if !MMU && RISCV_M_MODE

	default 0x80200000 if !MMU

	default 0xc0000000 if 32BIT

	default 0xff60000000000000 if 64BIT



config KASAN_SHADOW_OFFSET
@@ -597,7 +602,6 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO 
config RISCV_ISA_ZBB

	bool "Zbb extension support for bit manipulation instructions"

	depends on TOOLCHAIN_HAS_ZBB

	depends on MMU

	depends on RISCV_ALTERNATIVE

	default y

	help
@@ -629,7 +633,6 @@ config RISCV_ISA_ZICBOM 


config RISCV_ISA_ZICBOZ

	bool "Zicboz extension support for faster zeroing of memory"

	depends on MMU

	depends on RISCV_ALTERNATIVE

	default y

	help

arch/riscv/include/asm/page.h

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ typedef struct page *pgtable_t; 
#define PTE_FMT "%08lx"

#endif



#ifdef CONFIG_64BIT

#if defined(CONFIG_64BIT) && defined(CONFIG_MMU)

/*

 * We override this value as its generic definition uses __pa too early in

 * the boot process (before kernel_map.va_pa_offset is set).

arch/riscv/include/asm/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -890,7 +890,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) 
#define PAGE_SHARED		__pgprot(0)

#define PAGE_KERNEL		__pgprot(0)

#define swapper_pg_dir		NULL

#define TASK_SIZE		0xffffffffUL

#define TASK_SIZE		_AC(-1, UL)

#define VMALLOC_START		_AC(0, UL)

#define VMALLOC_END		TASK_SIZE

arch/riscv/mm/init.c

+1 −1
Original line number Diff line number Diff line
@@ -231,7 +231,7 @@ static void __init setup_bootmem(void) 
	 * In 64-bit, any use of __va/__pa before this point is wrong as we

	 * did not know the start of DRAM before.

	 */

	if (IS_ENABLED(CONFIG_64BIT))

	if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU))

		kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;



	/*