Commit d5272aaa authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: mm: fix new code about cache aliasing 

Manual/partial revert of 8690bbcf ("Introduce cpu_dcache_is_aliasing() across all architectures")

Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).

Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) [1] however recently that support was ripped out so VIPT aliasing
cache is not relevant to ARC anymore.

[1] http://lists.infradead.org/pipermail/linux-snps-arc/2023-February/006899.html



Acked-by: default avatarMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: default avatarVineet Gupta <vgupta@kernel.org>
parent db70d9f9

arch/arc/Kconfig

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@@ -6,7 +6,6 @@ 
config ARC

	def_bool y

	select ARC_TIMERS

	select ARCH_HAS_CPU_CACHE_ALIASING

	select ARCH_HAS_CACHE_LINE_SIZE

	select ARCH_HAS_DEBUG_VM_PGTABLE

	select ARCH_HAS_DMA_PREP_COHERENT

arch/arc/include/asm/cachetype.h

deleted100644 → 0
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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __ASM_ARC_CACHETYPE_H

#define __ASM_ARC_CACHETYPE_H



#include <linux/types.h>



#define cpu_dcache_is_aliasing()	true



#endif