Commit d5f9a92b authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Revert "Improve x86 and dmub ips handshake" 



This reverts commit 1288d702.

Causes intermittent hangs during reboot stress testing.

Reviewed-by: default avatarDuncan Ma <duncan.ma@amd.com>
Acked-by: default avatarRoman Li <roman.li@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 543068f0

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

+0 −37
Original line number Diff line number Diff line
@@ -808,34 +808,6 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base) 
	}

}



static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)

{

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	struct dc *dc = clk_mgr_base->ctx->dc;

	uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);



	if (dc->config.disable_ips == 0) {

		val |= DMUB_IPS1_ALLOW_MASK;

		val |= DMUB_IPS2_ALLOW_MASK;

	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {

		val = val & ~DMUB_IPS1_ALLOW_MASK;

		val = val & ~DMUB_IPS2_ALLOW_MASK;

	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {

		val |= DMUB_IPS1_ALLOW_MASK;

		val = val & ~DMUB_IPS2_ALLOW_MASK;

	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {

		val |= DMUB_IPS1_ALLOW_MASK;

		val |= DMUB_IPS2_ALLOW_MASK;

	}



	if (!allow_idle) {

		val = val & ~DMUB_IPS1_ALLOW_MASK;

		val = val & ~DMUB_IPS2_ALLOW_MASK;

	}



	dcn35_smu_write_ips_scratch(clk_mgr, val);

}



static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)

{

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
@@ -855,13 +827,6 @@ static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base) 
	return ips_supported;

}



static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)

{

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);



	return dcn35_smu_read_ips_scratch(clk_mgr);

}



static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)

{

	dcn35_init_clocks(clk_mgr);
@@ -949,8 +914,6 @@ static struct clk_mgr_funcs dcn35_funcs = { 
	.set_low_power_state = dcn35_set_low_power_state,

	.exit_low_power_state = dcn35_exit_low_power_state,

	.is_ips_supported = dcn35_is_ips_supported,

	.set_idle_state = dcn35_set_idle_state,

	.get_idle_state = dcn35_get_idle_state

};



struct clk_mgr_funcs dcn35_fpga_funcs = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

+2 −12
Original line number Diff line number Diff line
@@ -444,9 +444,9 @@ void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *cl 
			enable);

}



int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)

void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)

{

	return dcn35_smu_send_msg_with_param(

	dcn35_smu_send_msg_with_param(

		clk_mgr,

		VBIOSSMC_MSG_DispPsrExit,

		0);
@@ -459,13 +459,3 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr) 
			VBIOSSMC_MSG_QueryIPS2Support,

			0);

}
 


void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)

{

	REG_WRITE(MP1_SMN_C2PMSG_71, param);

}



uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)

{

	return REG_READ(MP1_SMN_C2PMSG_71);

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

+1 −3
Original line number Diff line number Diff line
@@ -194,10 +194,8 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst 
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);



int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);

void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);

int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);

int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);

int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);

void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param);

uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr);

#endif /* DAL_DC_35_SMU_H_ */

drivers/gpu/drm/amd/display/dc/dc.h

+0 −2
Original line number Diff line number Diff line
@@ -975,8 +975,6 @@ struct dc_debug_options { 
	bool replay_skip_crtc_disabled;

	bool ignore_pg;/*do nothing, let pmfw control it*/

	bool psp_disabled_wa;

	unsigned int ips2_eval_delay_us;

	unsigned int ips2_entry_delay_us;

};



struct gpu_info_soc_bounding_box_v1_0;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

+12 −45
Original line number Diff line number Diff line
@@ -1100,64 +1100,31 @@ void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle) 


	cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;



	if (allow_idle) {

		if (dc->hwss.set_idle_state)

			dc->hwss.set_idle_state(dc, true);

	}



	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);



	if (allow_idle)

		udelay(500);

}



void dc_dmub_srv_exit_low_power_state(const struct dc *dc)

{

	uint32_t allow_state = 0;

	uint32_t commit_state = 0;



	if (dc->debug.dmcub_emulation)

		return;



	if (!dc->idle_optimizations_allowed)

		return;



	if (dc->hwss.get_idle_state &&

		dc->hwss.set_idle_state &&

		dc->clk_mgr->funcs->exit_low_power_state) {



		allow_state = dc->hwss.get_idle_state(dc);

		dc->hwss.set_idle_state(dc, false);



		if (allow_state & DMUB_IPS2_ALLOW_MASK) {

			// Wait for evaluation time

			udelay(dc->debug.ips2_eval_delay_us);

			commit_state = dc->hwss.get_idle_state(dc);

			if (commit_state & DMUB_IPS2_COMMIT_MASK) {

	// Tell PMFW to exit low power state

	if (dc->clk_mgr->funcs->exit_low_power_state)

		dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);



				// Wait for IPS2 entry upper bound

				udelay(dc->debug.ips2_entry_delay_us);

				dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);



				do {

					commit_state = dc->hwss.get_idle_state(dc);

				} while (commit_state & DMUB_IPS2_COMMIT_MASK);



				if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

					ASSERT(0);



				return;

			}

		}

	// Wait for dmcub to load up

	dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);



	// Notify dmcub disallow idle

	dc_dmub_srv_notify_idle(dc, false);

		if (allow_state & DMUB_IPS1_ALLOW_MASK) {

			do {

				commit_state = dc->hwss.get_idle_state(dc);

			} while (commit_state & DMUB_IPS1_COMMIT_MASK);

		}

	}



	if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

		ASSERT(0);

	// Confirm dmu is powered up

	dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);

}