Commit d662a710 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "Core:
   - New devm_of_dma_controller_register() API

  New Support:
   - Support for RZ/G3L SoC
   - Loongson Multi-Channel DMA controller support
   - Conversion of Xilinx AXI DMA binding
   - DW AXI CV1800B DMA support
   - Switchtec DMA engine driver

  Updates:
   - AMD MDB Endpoint and non-LL mode support
   - DW edma virtual IRQ for interrupt-emulation, cyclic transfers support"

* tag 'dmaengine-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (65 commits)
  dmaengine: dw-edma: Add non-LL mode
  dmaengine: dw-edma: Add AMD MDB Endpoint Support
  dt-bindings: dmaengine: Fix spelling mistake "Looongson" -> "Looogson"
  dmaengine: loongson: Fix spelling mistake "Looongson" -> "Looogson"
  dmaengine: loongson: New driver for the Loongson Multi-Channel DMA controller
  dt-bindings: dmaengine: Add Loongson Multi-Channel DMA controller
  dmaengine: loongson: loongson2-apb: Simplify locking with guard() and scoped_guard()
  dmaengine: loongson: loongson2-apb: Convert to devm_clk_get_enabled()
  dmaengine: loongson: loongson2-apb: Convert to dmaenginem_async_device_register()
  dmaengine: loongson: New directory for Loongson DMA controllers drivers
  dt-bindings: dma: xlnx,axi-dma: Convert to DT schema
  dt-bindings: dma: rz-dmac: Add conditional schema for RZ/G3L
  dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks
  dmaengine: sh: rz-dmac: Add device_tx_status() callback
  dmaengine: sh: rz-dmac: Use rz_lmdesc_setup() to invalidate descriptors
  dmaengine: sh: rz-dmac: Drop unnecessary local_irq_save() call
  dmaengine: sh: rz-dmac: Drop goto instruction and label
  dmaengine: sh: rz-dmac: Drop read of CHCTRL register
  dmaengine: sh: rz_dmac: add RZ/{T2H,N2H} support
  dt-bindings: dma: renesas,rz-dmac: document RZ/{T2H,N2H}
  ...
parents 3f887edd b7560798

Documentation/devicetree/bindings/dma/loongson,ls2k0300-dma.yaml

0 → 100644
+81 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/loongson,ls2k0300-dma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Loongson-2 Multi-Channel DMA controller



description:

  The Loongson-2 Multi-Channel DMA controller is used for transferring data

  between system memory and the peripherals on the APB bus.



maintainers:

  - Binbin Zhou <zhoubinbin@loongson.cn>



allOf:

  - $ref: dma-controller.yaml#



properties:

  compatible:

    enum:

      - loongson,ls2k0300-dma

      - loongson,ls2k3000-dma



  reg:

    maxItems: 1



  interrupts:

    description:

      Should contain all of the per-channel DMA interrupts in ascending order

      with respect to the DMA channel index.

    minItems: 4

    maxItems: 8



  clocks:

    maxItems: 1



  '#dma-cells':

    const: 2

    description: |

      DMA request from clients consists of 2 cells:

        1. Channel index

        2. Transfer request factor number, If no transfer factor, use 0.

           The number is SoC-specific, and this should be specified with

           relation to the device to use the DMA controller.



  dma-channels:

    enum: [4, 8]



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - '#dma-cells'

  - dma-channels



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/loongson,ls2k-clk.h>



    dma-controller@1612c000 {

        compatible = "loongson,ls2k0300-dma";

        reg = <0x1612c000 0xff>;

        interrupt-parent = <&liointc0>;

        interrupts = <23 IRQ_TYPE_LEVEL_HIGH>,

                     <24 IRQ_TYPE_LEVEL_HIGH>,

                     <25 IRQ_TYPE_LEVEL_HIGH>,

                     <26 IRQ_TYPE_LEVEL_HIGH>,

                     <27 IRQ_TYPE_LEVEL_HIGH>,

                     <28 IRQ_TYPE_LEVEL_HIGH>,

                     <29 IRQ_TYPE_LEVEL_HIGH>,

                     <30 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clk LS2K0300_CLK_APB_GATE>;

        #dma-cells = <2>;

        dma-channels = <8>;

    };

...

Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml

+84 −18
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ properties: 
              - renesas,r9a07g044-dmac # RZ/G2{L,LC}

              - renesas,r9a07g054-dmac # RZ/V2L

              - renesas,r9a08g045-dmac # RZ/G3S

              - renesas,r9a08g046-dmac # RZ/G3L

          - const: renesas,rz-dmac



      - items:
@@ -29,6 +30,13 @@ properties: 


      - const: renesas,r9a09g057-dmac # RZ/V2H(P)



      - const: renesas,r9a09g077-dmac # RZ/T2H



      - items:

          - enum:

              - renesas,r9a09g087-dmac # RZ/N2H

          - const: renesas,r9a09g077-dmac



  reg:

    items:

      - description: Control and channel register block
@@ -36,27 +44,12 @@ properties: 
    minItems: 1



  interrupts:

    minItems: 16

    maxItems: 17



  interrupt-names:

    items:

      - const: error

      - const: ch0

      - const: ch1

      - const: ch2

      - const: ch3

      - const: ch4

      - const: ch5

      - const: ch6

      - const: ch7

      - const: ch8

      - const: ch9

      - const: ch10

      - const: ch11

      - const: ch12

      - const: ch13

      - const: ch14

      - const: ch15

    minItems: 16

    maxItems: 17



  clocks:

    items:
@@ -122,6 +115,35 @@ required: 
allOf:

  - $ref: dma-controller.yaml#



  - if:

      properties:

        compatible:

          contains:

            enum:

              - renesas,rz-dmac

              - renesas,r9a09g057-dmac

    then:

      properties:

        interrupt-names:

          items:

            - const: error

            - const: ch0

            - const: ch1

            - const: ch2

            - const: ch3

            - const: ch4

            - const: ch5

            - const: ch6

            - const: ch7

            - const: ch8

            - const: ch9

            - const: ch10

            - const: ch11

            - const: ch12

            - const: ch13

            - const: ch14

            - const: ch15



  - if:

      properties:

        compatible:
@@ -131,6 +153,7 @@ allOf: 
              - renesas,r9a07g044-dmac

              - renesas,r9a07g054-dmac

              - renesas,r9a08g045-dmac

              - renesas,r9a08g046-dmac

    then:

      properties:

        reg:
@@ -189,6 +212,49 @@ allOf: 
        - renesas,icu

        - resets



  - if:

      properties:

        compatible:

          contains:

            const: renesas,r9a09g077-dmac

    then:

      properties:

        reg:

          maxItems: 1

        clocks:

          maxItems: 1



        clock-names: false

        resets: false

        reset-names: false



        interrupts:

          maxItems: 16



        interrupt-names:

          items:

            - const: ch0

            - const: ch1

            - const: ch2

            - const: ch3

            - const: ch4

            - const: ch5

            - const: ch6

            - const: ch7

            - const: ch8

            - const: ch9

            - const: ch10

            - const: ch11

            - const: ch12

            - const: ch13

            - const: ch14

            - const: ch15



      required:

        - clocks

        - power-domains

        - renesas,icu



additionalProperties: false



examples:

Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml

+3 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ properties: 
      - enum:

          - snps,axi-dma-1.01a

          - intel,kmb-axi-dma

          - sophgo,cv1800b-axi-dma

          - starfive,jh7110-axi-dma

          - starfive,jh8100-axi-dma

      - items:
@@ -68,6 +69,8 @@ properties: 


  dma-noncoherent: true



  dma-coherent: true



  resets:

    minItems: 1

    maxItems: 2

Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

deleted100644 → 0
+0 −111
Original line number Diff line number Diff line 
Xilinx AXI VDMA engine, it does transfers between memory and video devices.

It can be configured to have one channel or two channels. If configured

as two channels, one is to transmit to the video device and another is

to receive from the video device.



Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream

target devices. It can be configured to have one channel or two channels.

If configured as two channels, one is to transmit to the device and another

is to receive from the device.



Xilinx AXI CDMA engine, it does transfers between memory-mapped source

address and a memory-mapped destination address.



Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream

target devices. It can be configured to have up to 16 independent transmit

and receive channels.



Required properties:

- compatible: Should be one of-

		"xlnx,axi-vdma-1.00.a"

		"xlnx,axi-dma-1.00.a"

		"xlnx,axi-cdma-1.00.a"

		"xlnx,axi-mcdma-1.00.a"

- #dma-cells: Should be <1>, see "dmas" property below

- reg: Should contain VDMA registers location and length.

- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).

- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.

- dma-channel child node: Should have at least one channel and can have up to

	two channels per device. This node specifies the properties of each

	DMA channel (see child node properties below).

- clocks: Input clock specifier. Refer to common clock bindings.

- clock-names: List of input clocks

	For VDMA:

	Required elements: "s_axi_lite_aclk"

	Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",

			   "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"

	For CDMA:

	Required elements: "s_axi_lite_aclk", "m_axi_aclk"

	For AXIDMA and MCDMA:

	Required elements: "s_axi_lite_aclk"

	Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",

			   "m_axi_sg_aclk"



Required properties for VDMA:

- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.



Optional properties for AXI DMA and MCDMA:

- xlnx,sg-length-width: Should be set to the width in bits of the length

	register as configured in h/w. Takes values {8...26}. If the property

	is missing or invalid then the default value 23 is used. This is the

	maximum value that is supported by all IP versions.



Optional properties for AXI DMA:

- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.

- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from

	0-255. Setting this value to zero disables the delay timer interrupt.

	1 timeout interval = 125 * clock period of SG clock.

Optional properties for VDMA:

- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.

	It takes following values:

	{1}, flush both channels

	{2}, flush mm2s channel

	{3}, flush s2mm channel



Required child node properties:

- compatible:

	For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or

	"xlnx,axi-vdma-s2mm-channel".

	For CDMA: It should be "xlnx,axi-cdma-channel".

	For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel"

	or "xlnx,axi-dma-s2mm-channel".

- interrupts: Should contain per channel VDMA interrupts.

- xlnx,datawidth: Should contain the stream data width, take values

	{32,64...1024}.



Optional child node properties:

- xlnx,include-dre: Tells hardware is configured for Data

	Realignment Engine.

Optional child node properties for VDMA:

- xlnx,genlock-mode: Tells Genlock synchronization is

	enabled/disabled in hardware.

- xlnx,enable-vert-flip: Tells vertical flip is

	enabled/disabled in hardware(S2MM path).

Optional child node properties for MCDMA:

- dma-channels: Number of dma channels in child node.



Example:

++++++++



axi_vdma_0: axivdma@40030000 {

	compatible = "xlnx,axi-vdma-1.00.a";

	#dma_cells = <1>;

	reg = < 0x40030000 0x10000 >;

	dma-ranges = <0x00000000 0x00000000 0x40000000>;

	xlnx,num-fstores = <0x8>;

	xlnx,flush-fsync = <0x1>;

	xlnx,addrwidth = <0x20>;

	clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;

	clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",

		      "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";

	dma-channel@40030000 {

		compatible = "xlnx,axi-vdma-mm2s-channel";

		interrupts = < 0 54 4 >;

		xlnx,datawidth = <0x40>;

	} ;

	dma-channel@40030030 {

		compatible = "xlnx,axi-vdma-s2mm-channel";

		interrupts = < 0 53 4 >;

		xlnx,datawidth = <0x40>;

	} ;

} ;

Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml

0 → 100644
+299 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/xilinx/xlnx,axi-dma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx AXI VDMA, DMA, CDMA and MCDMA IP



maintainers:

  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>

  - Abin Joseph <abin.joseph@amd.com>



description: >

  Xilinx AXI VDMA engine, it does transfers between memory and video devices.

  It can be configured to have one channel or two channels. If configured

  as two channels, one is to transmit to the video device and another is

  to receive from the video device.



  Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream

  target devices. It can be configured to have one channel or two channels.

  If configured as two channels, one is to transmit to the device and another

  is to receive from the device.



  Xilinx AXI CDMA engine, it does transfers between memory-mapped source

  address and a memory-mapped destination address.



  Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream

  target devices. It can be configured to have up to 16 independent transmit

  and receive channels.



properties:

  compatible:

    enum:

      - xlnx,axi-cdma-1.00.a

      - xlnx,axi-dma-1.00.a

      - xlnx,axi-mcdma-1.00.a

      - xlnx,axi-vdma-1.00.a



  reg:

    maxItems: 1



  "#dma-cells":

    const: 1



  "#address-cells":

    const: 1



  "#size-cells":

    const: 1



  interrupts:

    items:

      - description: Interrupt for single channel (MM2S or S2MM)

      - description: Interrupt for dual channel configuration

    minItems: 1

    description:

      Interrupt lines for the DMA controller. Only used when

      xlnx,axistream-connected is present (DMA connected to AXI Stream

      IP). When child dma-channel nodes are present, interrupts are

      specified in the child nodes instead.



  clocks:

    minItems: 1

    maxItems: 5



  clock-names:

    minItems: 1

    maxItems: 5



  dma-ranges: true



  xlnx,addrwidth:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [32, 64]

    description: The DMA addressing size in bits.



  xlnx,num-fstores:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1

    maximum: 32

    description: Should be the number of framebuffers as configured in h/w.



  xlnx,flush-fsync:

    type: boolean

    description: Tells which channel to Flush on Frame sync.



  xlnx,sg-length-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 8

    maximum: 26

    default: 23

    description:

      Width in bits of the length register as configured in hardware.



  xlnx,irq-delay:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0

    maximum: 255

    description:

      Tells the interrupt delay timeout value. Valid range is from 0-255.

      Setting this value to zero disables the delay timer interrupt.

      1 timeout interval = 125 * clock period of SG clock.



  xlnx,axistream-connected:

    type: boolean

    description: Tells whether DMA is connected to AXI stream IP.



patternProperties:

  "^dma-channel(-mm2s|-s2mm)?$":

    type: object

    description:

      Should have at least one channel and can have up to two channels per

      device. This node specifies the properties of each DMA channel.



    properties:

      compatible:

        enum:

          - xlnx,axi-vdma-mm2s-channel

          - xlnx,axi-vdma-s2mm-channel

          - xlnx,axi-cdma-channel

          - xlnx,axi-dma-mm2s-channel

          - xlnx,axi-dma-s2mm-channel



      interrupts:

        maxItems: 1



      xlnx,datawidth:

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [32, 64, 128, 256, 512, 1024]

        description: Should contain the stream data width, take values {32,64...1024}.



      xlnx,include-dre:

        type: boolean

        description: Tells hardware is configured for Data Realignment Engine.



      xlnx,genlock-mode:

        type: boolean

        description: Tells Genlock synchronization is enabled/disabled in hardware.



      xlnx,enable-vert-flip:

        type: boolean

        description:

          Tells vertical flip is enabled/disabled in hardware(S2MM path).



      dma-channels:

        $ref: /schemas/types.yaml#/definitions/uint32

        description: Number of dma channels in child node.



    required:

      - compatible

      - interrupts

      - xlnx,datawidth



    additionalProperties: false



allOf:

  - $ref: ../dma-controller.yaml#



  - if:

      properties:

        compatible:

          contains:

            const: xlnx,axi-vdma-1.00.a

    then:

      properties:

        clock-names:

          items:

            - const: s_axi_lite_aclk

            - const: m_axi_mm2s_aclk

            - const: m_axi_s2mm_aclk

            - const: m_axis_mm2s_aclk

            - const: s_axis_s2mm_aclk

          minItems: 1

        interrupts: false

      patternProperties:

        "^dma-channel(-mm2s|-s2mm)?$":

          properties:

            compatible:

              enum:

                - xlnx,axi-vdma-mm2s-channel

                - xlnx,axi-vdma-s2mm-channel

      required:

        - xlnx,num-fstores



  - if:

      properties:

        compatible:

          contains:

            const: xlnx,axi-cdma-1.00.a

    then:

      properties:

        clock-names:

          items:

            - const: s_axi_lite_aclk

            - const: m_axi_aclk

        interrupts: false

      patternProperties:

        "^dma-channel(-mm2s|-s2mm)?$":

          properties:

            compatible:

              enum:

                - xlnx,axi-cdma-channel



  - if:

      properties:

        compatible:

          contains:

            enum:

              - xlnx,axi-dma-1.00.a

              - xlnx,axi-mcdma-1.00.a

    then:

      properties:

        clock-names:

          items:

            - const: s_axi_lite_aclk

            - const: m_axi_mm2s_aclk

            - const: m_axi_s2mm_aclk

            - const: m_axi_sg_aclk

          minItems: 1

      patternProperties:

        "^dma-channel(-mm2s|-s2mm)?(@[0-9a-f]+)?$":

          properties:

            compatible:

              enum:

                - xlnx,axi-dma-mm2s-channel

                - xlnx,axi-dma-s2mm-channel



required:

  - "#dma-cells"

  - reg

  - xlnx,addrwidth

  - dma-ranges

  - clocks

  - clock-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    dma-controller@40030000 {

        compatible = "xlnx,axi-vdma-1.00.a";

        reg = <0x40030000 0x10000>;

        #dma-cells = <1>;

        #address-cells = <1>;

        #size-cells = <1>;

        dma-ranges = <0x0 0x0 0x40000000>;

        clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;

        clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",

                      "m_axi_s2mm_aclk", "m_axis_mm2s_aclk",

                      "s_axis_s2mm_aclk";

        xlnx,num-fstores = <8>;

        xlnx,flush-fsync;

        xlnx,addrwidth = <32>;



        dma-channel-mm2s {

            compatible = "xlnx,axi-vdma-mm2s-channel";

            interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

            xlnx,datawidth = <64>;

        };



        dma-channel-s2mm {

            compatible = "xlnx,axi-vdma-s2mm-channel";

            interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

            xlnx,datawidth = <64>;

        };

    };



  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    dma-controller@a4030000 {

        compatible = "xlnx,axi-dma-1.00.a";

        reg = <0xa4030000 0x10000>;

        #dma-cells = <1>;

        #address-cells = <1>;

        #size-cells = <1>;

        dma-ranges = <0x0 0x0 0x40000000>;

        clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>;

        clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",

                      "m_axi_s2mm_aclk", "m_axi_sg_aclk";

        xlnx,addrwidth = <32>;

        xlnx,sg-length-width = <14>;



        dma-channel-mm2s {

            compatible = "xlnx,axi-dma-mm2s-channel";

            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

            xlnx,datawidth = <64>;

            xlnx,include-dre;

        };



        dma-channel-s2mm {

            compatible = "xlnx,axi-dma-s2mm-channel";

            interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

            xlnx,datawidth = <64>;

            xlnx,include-dre;

        };

    };