Commit d70ccd4a authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: Keep blank until set visibility to true after mode switch 



Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e75504b1

drivers/gpu/drm/amd/display/dc/core/dc.c

+9 −12
Original line number Diff line number Diff line
@@ -1609,13 +1609,11 @@ void dc_update_surfaces_and_stream(struct dc *dc, 
			if (!pipe_ctx->surface || pipe_ctx->top_pipe)

				continue;



			if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {

			core_dc->hwss.pipe_control_lock(

					core_dc,

					pipe_ctx,

					true);

		}

		}

		if (update_type == UPDATE_TYPE_FULL)

			break;

	}
@@ -1697,12 +1695,11 @@ void dc_update_surfaces_and_stream(struct dc *dc, 
			if (!pipe_ctx->surface || pipe_ctx->top_pipe)

				continue;



			if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {

			core_dc->hwss.pipe_control_lock(

					core_dc,

					pipe_ctx,

					false);

			}



			break;

		}

	}

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c

+4 −0
Original line number Diff line number Diff line
@@ -52,6 +52,10 @@ void dce_pipe_control_lock(struct core_dc *dc, 
	uint32_t dcp_grph, scl, blnd, update_lock_mode, val;

	struct dce_hwseq *hws = dc->hwseq;



	/* Not lock pipe when blank */

	if (lock && pipe->tg->funcs->is_blanked(pipe->tg))

		return;



	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],

			BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,

			BLND_SCL_V_UPDATE_LOCK, &scl,