Commit d7767a1f authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/vcn3: implement ring reset 



Use the new helpers to handle engine resets for VCN.

Reviewed-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 63b8c9fd

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+27 −0
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 
				 enum amd_powergating_state state);

static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,

				   struct dpg_pause_state *new_state);

static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst);



static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);

static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
@@ -289,8 +290,14 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 


		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)

			adev->vcn.inst[i].pause_dpg_mode = vcn_v3_0_pause_dpg_mode;

		adev->vcn.inst[i].reset = vcn_v3_0_reset;

	}



	adev->vcn.supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

	if (!amdgpu_sriov_vf(adev))

		adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;



	if (amdgpu_sriov_vf(adev)) {

		r = amdgpu_virt_alloc_mm_table(adev);

		if (r)
@@ -306,6 +313,10 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 
		adev->vcn.ip_dump = ptr;

	}



	r = amdgpu_vcn_sysfs_reset_mask_init(adev);

	if (r)

		return r;



	return 0;

}
@@ -338,6 +349,8 @@ static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) 
	if (amdgpu_sriov_vf(adev))

		amdgpu_virt_free_mm_table(adev);



	amdgpu_vcn_sysfs_reset_mask_fini(adev);



	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		r = amdgpu_vcn_suspend(adev, i);

		if (r)
@@ -2033,6 +2046,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 
	.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,

	.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,

	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

	.reset = amdgpu_vcn_ring_reset,

};



/**
@@ -2131,6 +2145,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 
	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,

	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,

	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

	.reset = amdgpu_vcn_ring_reset,

};



static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
@@ -2164,6 +2179,18 @@ static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 
	}

}



static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst)

{

	int r;



	r = vcn_v3_0_stop(vinst);

	if (r)

		return r;

	vcn_v3_0_enable_clock_gating(vinst);

	vcn_v3_0_enable_static_power_gating(vinst);

	return vcn_v3_0_start(vinst);

}



static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = ip_block->adev;