Commit d9e697f1 authored by Shashank Sharma's avatar Shashank Sharma Committed by Alex Deucher
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drm/amdgpu: bypass SRIOV check for shadow size info 



Currently, the shadow FW space size and alignment information is
protected under a flag (adev->gfx.cp_gfx_shadow) which gets set
only in case of SRIOV setups.
if (amdgpu_sriov_vf(adev))
    adev->gfx.cp_gfx_shadow = true;

But we need this information for GFX Userqueues, so that user can
create these objects while creating userqueue. This patch series
creates a method to get this information bypassing the dependency
on this check.

This patch:
- adds a new input parameter flag to the gfx.funcs->get_gfx_shadow_info
fptr definition, so that it can accommodate the information without the
check (adev->gfx.cp_gfx_shadow) on request.
- updates the existing definition of amdgpu_gfx_get_gfx_shadow_info to
adjust with this new flag.

Next patch in the series is adding a UAPI which will consume this info.

V2: split this patch from the new UAPI patch

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Arvind Yadav <arvind.yadav@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarShashank Sharma <shashank.sharma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2e06b175

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+3 −2
Original line number Diff line number Diff line
@@ -305,7 +305,8 @@ struct amdgpu_gfx_funcs { 
	void (*init_spm_golden)(struct amdgpu_device *adev);

	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);

	int (*get_gfx_shadow_info)(struct amdgpu_device *adev,

				   struct amdgpu_gfx_shadow_info *shadow_info);

				   struct amdgpu_gfx_shadow_info *shadow_info,

				   bool skip_check);

	enum amdgpu_gfx_partition

			(*query_partition_mode)(struct amdgpu_device *adev);

	int (*switch_partition_mode)(struct amdgpu_device *adev,
@@ -503,7 +504,7 @@ struct amdgpu_gfx_ras_mem_id_entry { 
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))

#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))

#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))

#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si)))

#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si), false))



/**

 * amdgpu_gfx_create_bitmask - create a bitmask

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+13 −6
Original line number Diff line number Diff line
@@ -1086,14 +1086,21 @@ static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 
#define MQD_FWWORKAREA_SIZE       484

#define MQD_FWWORKAREA_ALIGNMENT  256



static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,

static void gfx_v11_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev,

					 struct amdgpu_gfx_shadow_info *shadow_info)

{

	if (adev->gfx.cp_gfx_shadow) {

	shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;

	shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;

	shadow_info->csa_size = MQD_FWWORKAREA_SIZE;

	shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;

}



static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,

					 struct amdgpu_gfx_shadow_info *shadow_info,

					 bool skip_check)

{

	if (adev->gfx.cp_gfx_shadow || skip_check) {

		gfx_v11_0_get_gfx_shadow_info_nocheck(adev, shadow_info);

		return 0;

	} else {

		memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));