Commit dc6061ed authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/brcmstb' 

- Add optional DT 'num-lanes' property and if present, use it to override
  the Maximum Link Width advertised in Link Capabilities (Jim Quinlan)

* pci/controller/brcmstb:
  PCI: brcmstb: Replace open coded value with PCIE_T_RRS_READY_MS
  MAINTAINERS: Drop Nicolas from maintaining pcie-brcmstb
  PCI: brcmstb: Set MLW based on "num-lanes" DT property if present
  dt-bindings: PCI: brcm,stb-pcie: Add num-lanes property
parents 480b3153 e8e7c1e9

Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml

+4 −0
Original line number Diff line number Diff line
@@ -107,6 +107,10 @@ properties: 
      - const: bridge

      - const: swinit



  num-lanes:

    default: 1

    maximum: 4



required:

  - compatible

  - reg

MAINTAINERS

+0 −1
Original line number Diff line number Diff line
@@ -5085,7 +5085,6 @@ F: include/linux/platform_data/brcmnand.h 








BROADCOM STB PCIE DRIVER









M:	Jim Quinlan <jim2101024@gmail.com>









M:	Nicolas Saenz Julienne <nsaenz@kernel.org>









M:	Florian Fainelli <florian.fainelli@broadcom.com>









R:	Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>









L:	linux-pci@vger.kernel.org
































drivers/pci/controller/pcie-brcmstb.c



+27
−6






























Original line number
Diff line number
Diff line







@@ -47,6 +47,7 @@







#define  PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK	0xffffff



















#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY			0x04dc









#define  PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK	0x1f0









#define  PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK	0xc00



















#define PCIE_RC_CFG_PRIV1_ROOT_CAP			0x4f8








@@ -56,6 +57,9 @@







#define PCIE_RC_DL_MDIO_WR_DATA				0x1104









#define PCIE_RC_DL_MDIO_RD_DATA				0x1108



















#define PCIE_RC_PL_REG_PHY_CTL_1			0x1804









#define  PCIE_RC_PL_REG_PHY_CTL_1_REG_P2_POWERDOWN_ENA_NOSYNC_MASK	0x8



















#define PCIE_RC_PL_PHY_CTL_15				0x184c









#define  PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK		0x400000









#define  PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK	0xff








@@ -1071,7 +1075,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)







	void __iomem *base = pcie->base;









	struct pci_host_bridge *bridge;









	struct resource_entry *entry;









	u32 tmp, burst, aspm_support;









	u32 tmp, burst, aspm_support, num_lanes, num_lanes_cap;









	u8 num_out_wins = 0;









	int num_inbound_wins = 0;









	int memc, ret;








@@ -1179,6 +1183,27 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)







		PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);









	writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);



















	/* 'tmp' still holds the contents of PRIV1_LINK_CAPABILITY */









	num_lanes_cap = u32_get_bits(tmp, PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK);









	num_lanes = 0;



















	/*









	 * Use hardware negotiated Max Link Width value by default.  If the









	 * "num-lanes" DT property is present, assume that the chip's default









	 * link width capability information is incorrect/undesired and use the









	 * specified value instead.









	 */









	if (!of_property_read_u32(pcie->np, "num-lanes", &num_lanes) &&









	    num_lanes && num_lanes <= 4 && num_lanes_cap != num_lanes) {









		u32p_replace_bits(&tmp, num_lanes,









			PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK);









		writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);









		tmp = readl(base + PCIE_RC_PL_REG_PHY_CTL_1);









		u32p_replace_bits(&tmp, 1,









			PCIE_RC_PL_REG_PHY_CTL_1_REG_P2_POWERDOWN_ENA_NOSYNC_MASK);









		writel(tmp, base + PCIE_RC_PL_REG_PHY_CTL_1);









	}



















	/*









	 * For config space accesses on the RC, show the right class for









	 * a PCIe-PCIe bridge (the default setting is to be EP mode).








@@ -1332,11 +1357,7 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie)







	if (ret)









		return ret;



















	/*









	 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification









	 * sections 2.2, PCIe r5.0, 6.6.1.









	 */









	msleep(100);









	msleep(PCIE_RESET_CONFIG_WAIT_MS);



















	/*









	 * Give the RC/EP even more time to wake up, before trying to