Commit dd73925e authored by Animesh Manna's avatar Animesh Manna
Browse files

drm/i915/alpm: Move alpm parameters from intel_psr 



ALPM can be enabled for non psr panel and currenly aplm-params are
encapsulated under intel_psr struct, so moving out to intel_dp struct.

Reviewed-by: default avatarJouni Högander <jouni.hogander@intel.com>
Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-2-animesh.manna@intel.com
parent ed43c40e

drivers/gpu/drm/i915/display/intel_display_types.h

+10 −11
Original line number Diff line number Diff line
@@ -1705,17 +1705,6 @@ struct intel_psr { 
	bool psr2_sel_fetch_cff_enabled;

	bool req_psr2_sdp_prior_scanline;

	u8 sink_sync_latency;



	struct {

		u8 io_wake_lines;

		u8 fast_wake_lines;



		/* LNL and beyond */

		u8 check_entry_lines;

		u8 silence_period_sym_clocks;

		u8 lfps_half_cycle_num_of_syms;

	} alpm_parameters;



	ktime_t last_entry_attempt;

	ktime_t last_exit;

	bool sink_not_reliable;
@@ -1847,6 +1836,16 @@ struct intel_dp { 
	unsigned long last_oui_write;



	bool colorimetry_support;



	struct {

		u8 io_wake_lines;

		u8 fast_wake_lines;



		/* LNL and beyond */

		u8 check_entry_lines;

		u8 silence_period_sym_clocks;

		u8 lfps_half_cycle_num_of_syms;

	} alpm_parameters;

};



enum lspcon_vendor {

drivers/gpu/drm/i915/display/intel_psr.c

+21 −23
Original line number Diff line number Diff line
@@ -864,8 +864,8 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 


static int psr2_block_count_lines(struct intel_dp *intel_dp)

{

	return intel_dp->psr.alpm_parameters.io_wake_lines < 9 &&

		intel_dp->psr.alpm_parameters.fast_wake_lines < 9 ? 8 : 12;

	return intel_dp->alpm_parameters.io_wake_lines < 9 &&

		intel_dp->alpm_parameters.fast_wake_lines < 9 ? 8 : 12;

}



static int psr2_block_count(struct intel_dp *intel_dp)
@@ -903,7 +903,6 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp) 
static void hsw_activate_psr2(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct intel_psr *psr = &intel_dp->psr;

	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

	u32 val = EDP_PSR2_ENABLE;

	u32 psr_val = 0;
@@ -945,20 +944,20 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
		 */

		int tmp;



		tmp = map[psr->alpm_parameters.io_wake_lines -

		tmp = map[intel_dp->alpm_parameters.io_wake_lines -

			  TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];

		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES);



		tmp = map[psr->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];

		tmp = map[intel_dp->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];

		val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);

	} else if (DISPLAY_VER(dev_priv) >= 20) {

		val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);

		val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);

	} else if (DISPLAY_VER(dev_priv) >= 12) {

		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);

		val |= TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);

		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);

		val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines);

	} else if (DISPLAY_VER(dev_priv) >= 9) {

		val |= EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);

		val |= EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);

		val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);

		val |= EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines);

	}



	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
@@ -1341,9 +1340,9 @@ static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, 
	if (i915->display.params.psr_safest_params)

		aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;



	intel_dp->psr.alpm_parameters.fast_wake_lines = aux_less_wake_lines;

	intel_dp->psr.alpm_parameters.silence_period_sym_clocks = silence_period;

	intel_dp->psr.alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;

	intel_dp->alpm_parameters.fast_wake_lines = aux_less_wake_lines;

	intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period;

	intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;



	return true;

}
@@ -1370,7 +1369,7 @@ static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, 
	if (i915->display.params.psr_safest_params)

		check_entry_lines = 15;



	intel_dp->psr.alpm_parameters.check_entry_lines = check_entry_lines;

	intel_dp->alpm_parameters.check_entry_lines = check_entry_lines;



	return true;

}
@@ -1439,8 +1438,8 @@ static bool _compute_alpm_params(struct intel_dp *intel_dp, 
		io_wake_lines = fast_wake_lines = max_wake_lines;



	/* According to Bspec lower limit should be set as 7 lines. */

	intel_dp->psr.alpm_parameters.io_wake_lines = max(io_wake_lines, 7);

	intel_dp->psr.alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);

	intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7);

	intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);



	return true;

}
@@ -1841,7 +1840,6 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) 
{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

	struct intel_psr *psr = &intel_dp->psr;

	u32 alpm_ctl;



	if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled &&
@@ -1863,23 +1861,23 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) 
			       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |

			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |

			       PORT_ALPM_CTL_SILENCE_PERIOD(

				       psr->alpm_parameters.silence_period_sym_clocks));

				       intel_dp->alpm_parameters.silence_period_sym_clocks));



		intel_de_write(dev_priv,

			       PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder),

			       PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |

			       PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(

				       psr->alpm_parameters.lfps_half_cycle_num_of_syms) |

				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |

			       PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(

				       psr->alpm_parameters.lfps_half_cycle_num_of_syms) |

				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |

			       PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(

				       psr->alpm_parameters.lfps_half_cycle_num_of_syms));

				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms));

	} else {

		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |

			ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines);

			ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);

	}



	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines);

	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);



	intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl);

}