Commit de56f781 authored by Justin Swartz's avatar Justin Swartz Committed by Thomas Bogendoerfer
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mips: dts: ralink: mt7621: reorder pci?_phy attributes 



Reorder the attributes of the PCIe PHY nodes node to match
what the DTS style guide recommends.

Signed-off-by: default avatarJustin Swartz <justin.swartz@risingedge.co.za>
Reviewed-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent fdcb4f10

arch/mips/boot/dts/ralink/mt7621.dtsi

+6 −2
Original line number Diff line number Diff line
@@ -583,14 +583,18 @@ pcie@2,0 { 
	pcie0_phy: pcie-phy@1e149000 {

		compatible = "mediatek,mt7621-pci-phy";

		reg = <0x1e149000 0x0700>;

		clocks = <&sysc MT7621_CLK_XTAL>;



		#phy-cells = <1>;



		clocks = <&sysc MT7621_CLK_XTAL>;

	};



	pcie2_phy: pcie-phy@1e14a000 {

		compatible = "mediatek,mt7621-pci-phy";

		reg = <0x1e14a000 0x0700>;

		clocks = <&sysc MT7621_CLK_XTAL>;



		#phy-cells = <1>;



		clocks = <&sysc MT7621_CLK_XTAL>;

	};

};