Unverified Commit de70b532 authored by Yunhui Cui's avatar Yunhui Cui Committed by Alexandre Ghiti
Browse files

RISC-V: Enable cbo.clean/flush in usermode 



Enabling cbo.clean and cbo.flush in user mode makes it more
convenient to manage the cache state and achieve better performance.

Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarYunhui Cui <cuiyunhui@bytedance.com>
Link: https://lore.kernel.org/r/20250226063206.71216-2-cuiyunhui@bytedance.com


Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
parent 2f2cd9f3

arch/riscv/kernel/cpufeature.c

+8 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#define NUM_ALPHA_EXTS ('z' - 'a' + 1)



static bool any_cpu_has_zicboz;

static bool any_cpu_has_zicbom;



unsigned long elf_hwcap __read_mostly;
@@ -100,6 +101,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data, 
		pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");

		return -EINVAL;

	}



	any_cpu_has_zicbom = true;

	return 0;

}
@@ -1036,6 +1039,11 @@ void __init riscv_user_isa_enable(void) 
		current->thread.envcfg |= ENVCFG_CBZE;

	else if (any_cpu_has_zicboz)

		pr_warn("Zicboz disabled as it is unavailable on some harts\n");



	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM))

		current->thread.envcfg |= ENVCFG_CBCFE;

	else if (any_cpu_has_zicbom)

		pr_warn("Zicbom disabled as it is unavailable on some harts\n");

}



#ifdef CONFIG_RISCV_ALTERNATIVE