Commit df190e67 authored by Jiadong Zhu's avatar Jiadong Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/sdma6: split out per instance resume function 



Extract the resume sequence for individual sdma instance from sdma_v6_0_gfx_resume.
The function could be used for start/restart scenario on a certain instance.

Signed-off-by: default avatarJiadong Zhu <Jiadong.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ced65deb

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

+131 −109
Original line number Diff line number Diff line
@@ -469,14 +469,16 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 
}



/**

 * sdma_v6_0_gfx_resume - setup and start the async dma engines

 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine

 *

 * @adev: amdgpu_device pointer

 * @i: instance

 * @restore: used to restore wptr when restart

 *

 * Set up the gfx DMA ring buffers and enable them.

 * Returns 0 for success, error for failure.

 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.

 * Return 0 for success.

 */

static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)

static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)

{

	struct amdgpu_ring *ring;

	u32 rb_cntl, ib_cntl;
@@ -485,11 +487,8 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 
	u32 doorbell_offset;

	u32 temp;

	u64 wptr_gpu_addr;

	int i, r;



	for (i = 0; i < adev->sdma.num_instances; i++) {

	ring = &adev->sdma.instance[i].ring;



	if (!amdgpu_sriov_vf(adev))

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
@@ -506,11 +505,17 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 
	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);



	/* Initialize the ring buffer's read and write pointers */

	if (restore) {

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

	} else {

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);



	}

	/* setup the wptr shadow polling */

	wptr_gpu_addr = ring->wptr_gpu_addr;

	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
@@ -531,6 +536,7 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 
	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);



	if (!restore)

		ring->wptr = 0;



	/* before programing wptr to a less value, need set minor_ptr_update first */
@@ -610,7 +616,23 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 
	if (amdgpu_sriov_vf(adev))

		sdma_v6_0_enable(adev, true);



		r = amdgpu_ring_test_helper(ring);

	return amdgpu_ring_test_helper(ring);

}



/**

 * sdma_v6_0_gfx_resume - setup and start the async dma engines

 *

 * @adev: amdgpu_device pointer

 *

 * Set up the gfx DMA ring buffers and enable them.

 * Returns 0 for success, error for failure.

 */

static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)

{

	int i, r;



	for (i = 0; i < adev->sdma.num_instances; i++) {

		r = sdma_v6_0_gfx_resume_instance(adev, i, false);

		if (r)

			return r;

	}