Commit df205970 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge tag 'trbe-cortex-a510-errata' of... 


Merge tag 'trbe-cortex-a510-errata' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux into for-next/fixes

coresight: trbe: Workaround Cortex-A510 erratas

This pull request is providing arm64 definitions to support
TRBE Cortex-A510 erratas.

Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>

* tag 'trbe-cortex-a510-errata' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux:
  arm64: errata: Add detection for TRBE trace data corruption
  arm64: errata: Add detection for TRBE invalid prohibited states
  arm64: errata: Add detection for TRBE ignored system register writes
  arm64: Add Cortex-A510 CPU part definition
parents 9ae279ec 708e8af4

Documentation/arm64/silicon-errata.rst

+6 −0
Original line number Diff line number Diff line
@@ -52,6 +52,12 @@ stable kernels. 
| Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2064142        | ARM64_ERRATUM_2064142       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2038923        | ARM64_ERRATUM_2038923       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #1902691        | ARM64_ERRATUM_1902691       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |

arch/arm64/Kconfig

+59 −0
Original line number Diff line number Diff line
@@ -778,6 +778,65 @@ config ARM64_ERRATUM_2224489 


	  If unsure, say Y.



config ARM64_ERRATUM_2064142

	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.



	  Affected Cortex-A510 core might fail to write into system registers after the

	  TRBE has been disabled. Under some conditions after the TRBE has been disabled

	  writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,

	  and TRBTRG_EL1 will be ignored and will not be effected.



	  Work around this in the driver by executing TSB CSYNC and DSB after collection

	  is stopped and before performing a system register write to one of the affected

	  registers.



	  If unsure, say Y.



config ARM64_ERRATUM_2038923

	bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 2038923.



	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is

	  prohibited within the CPU. As a result, the trace buffer or trace buffer state

	  might be corrupted. This happens after TRBE buffer has been enabled by setting

	  TRBLIMITR_EL1.E, followed by just a single context synchronization event before

	  execution changes from a context, in which trace is prohibited to one where it

	  isn't, or vice versa. In these mentioned conditions, the view of whether trace

	  is prohibited is inconsistent between parts of the CPU, and the trace buffer or

	  the trace buffer state might be corrupted.



	  Work around this in the driver by preventing an inconsistent view of whether the

	  trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a

	  change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or

	  two ISB instructions if no ERET is to take place.



	  If unsure, say Y.



config ARM64_ERRATUM_1902691

	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.



	  Affected Cortex-A510 core might cause trace data corruption, when being written

	  into the memory. Effectively TRBE is broken and hence cannot be used to capture

	  trace data.



	  Work around this problem in the driver by just preventing TRBE initialization on

	  affected cpus. The firmware must have disabled the access to TRBE for the kernel

	  on such implementations. This will cover the kernel for any firmware that doesn't

	  do this already.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ 
#define ARM_CPU_PART_CORTEX_A76		0xD0B

#define ARM_CPU_PART_NEOVERSE_N1	0xD0C

#define ARM_CPU_PART_CORTEX_A77		0xD0D

#define ARM_CPU_PART_CORTEX_A510	0xD46

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_CORTEX_X2		0xD48

#define ARM_CPU_PART_NEOVERSE_N2	0xD49
@@ -116,6 +117,7 @@ 
#define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)

#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)

#define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)

#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

arch/arm64/kernel/cpu_errata.c

+27 −0
Original line number Diff line number Diff line
@@ -599,6 +599,33 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,

		CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_2064142

	{

		.desc = "ARM erratum 2064142",

		.capability = ARM64_WORKAROUND_2064142,



		/* Cortex-A510 r0p0 - r0p2 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_2038923

	{

		.desc = "ARM erratum 2038923",

		.capability = ARM64_WORKAROUND_2038923,



		/* Cortex-A510 r0p0 - r0p2 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1902691

	{

		.desc = "ARM erratum 1902691",

		.capability = ARM64_WORKAROUND_1902691,



		/* Cortex-A510 r0p0 - r0p1 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)

	},

#endif

	{

	}

arch/arm64/tools/cpucaps

+3 −0
Original line number Diff line number Diff line
@@ -55,6 +55,9 @@ WORKAROUND_1418040 
WORKAROUND_1463225

WORKAROUND_1508412

WORKAROUND_1542419

WORKAROUND_2064142

WORKAROUND_2038923

WORKAROUND_1902691

WORKAROUND_TRBE_OVERWRITE_FILL_MODE

WORKAROUND_TSB_FLUSH_FAILURE

WORKAROUND_TRBE_WRITE_OUT_OF_RANGE