Commit e126aa3a authored by Minda Chen's avatar Minda Chen Committed by Conor Dooley
Browse files

riscv: dts: starfive: Add USB dts node for JH7110 



Add USB wrapper layer and Cadence USB3 controller dts
configuration for StarFive JH7110 SoC and VisionFive2
Board.

Signed-off-by: default avatarMinda Chen <minda.chen@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent c2a10081

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -273,6 +273,11 @@ &uart0 { 
	status = "okay";

};



&usb0 {

	dr_mode = "peripheral";

	status = "okay";

};



&U74_1 {

	cpu-supply = <&vdd_cpu>;

};

arch/riscv/boot/dts/starfive/jh7110.dtsi

+32 −0
Original line number Diff line number Diff line
@@ -446,6 +446,38 @@ i2c2: i2c@10050000 { 
			status = "disabled";

		};



		usb0: usb@10100000 {

			compatible = "starfive,jh7110-usb";

			ranges = <0x0 0x0 0x10100000 0x100000>;

			#address-cells = <1>;

			#size-cells = <1>;

			starfive,stg-syscon = <&stg_syscon 0x4>;

			clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,

				 <&stgcrg JH7110_STGCLK_USB0_STB>,

				 <&stgcrg JH7110_STGCLK_USB0_APB>,

				 <&stgcrg JH7110_STGCLK_USB0_AXI>,

				 <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;

			clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";

			resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,

				 <&stgcrg JH7110_STGRST_USB0_APB>,

				 <&stgcrg JH7110_STGRST_USB0_AXI>,

				 <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;

			reset-names = "pwrup", "apb", "axi", "utmi_apb";

			status = "disabled";



			usb_cdns3: usb@0 {

				compatible = "cdns,usb3";

				reg = <0x0 0x10000>,

				      <0x10000 0x10000>,

				      <0x20000 0x10000>;

				reg-names = "otg", "xhci", "dev";

				interrupts = <100>, <108>, <110>;

				interrupt-names = "host", "peripheral", "otg";

				phys = <&usbphy0>;

				phy-names = "cdns3,usb2-phy";

			};

		};



		usbphy0: phy@10200000 {

			compatible = "starfive,jh7110-usb-phy";

			reg = <0x0 0x10200000 0x0 0x10000>;