Commit e2685ef5 authored by Jianbo Liu's avatar Jianbo Liu Committed by Leon Romanovsky
Browse files

net/mlx5: Add support for MRTCQ register 



Management Real Time Clock Query (MRTCQ) register is used to query
hardware clock identity.

Signed-off-by: default avatarJianbo Liu <jianbol@nvidia.com>
Reviewed-by: default avatarDragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20250109204231.1809851-3-tariqt@nvidia.com


Reviewed-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Reviewed-by: default avatarKalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent 387bef82

include/linux/mlx5/driver.h

+1 −0
Original line number Diff line number Diff line
@@ -160,6 +160,7 @@ enum { 
	MLX5_REG_MIRC		 = 0x9162,

	MLX5_REG_MTPTM		 = 0x9180,

	MLX5_REG_MTCTR		 = 0x9181,

	MLX5_REG_MRTCQ		 = 0x9182,

	MLX5_REG_SBCAM		 = 0xB01F,

	MLX5_REG_RESOURCE_DUMP   = 0xC000,

	MLX5_REG_DTOR            = 0xC00E,

include/linux/mlx5/mlx5_ifc.h

+10 −1
Original line number Diff line number Diff line
@@ -10680,7 +10680,8 @@ struct mlx5_ifc_mcam_access_reg_bits3 { 


	u8         regs_63_to_32[0x20];



	u8         regs_31_to_2[0x1e];

	u8         regs_31_to_3[0x1d];

	u8         mrtcq[0x1];

	u8         mtctr[0x1];

	u8         mtptm[0x1];

};
@@ -13171,4 +13172,12 @@ struct mlx5_ifc_msees_reg_bits { 
	u8         reserved_at_80[0x180];

};



struct mlx5_ifc_mrtcq_reg_bits {

	u8         reserved_at_0[0x40];



	u8         rt_clock_identity[0x40];



	u8         reserved_at_80[0x180];

};



#endif /* MLX5_IFC_H */