Commit e2dcc248 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

Merge tag 'renesas-fixes-for-v7.0-tag1' of... 

Merge tag 'renesas-fixes-for-v7.0-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes

Renesas fixes for v7.0

  - Fix SD card initialization on the RZ/T2H and RZ/N2H EVK boards,
  - Remove WDT nodes meant for other CPU cores on the RZ/V2H(P) SoC,
  - Fix Clock Pulse Generator registers on the RZ/T2H and RZ/N2H SoCs,
  - Fix Versa3-related boot hangs on the RZ/G3S SoM,
  - Fix Extended SPI interrupts on the R-Car X5H SoC.

* tag 'renesas-fixes-for-v7.0-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel

:
  arm64: dts: renesas: r8a78000: Fix out-of-range SPI interrupt numbers
  arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2
  arm64: dts: renesas: r9a09g087: Fix CPG register region sizes
  arm64: dts: renesas: r9a09g077: Fix CPG register region sizes
  arm64: dts: renesas: r9a09g057: Remove wdt{0,2,3} nodes
  arm64: dts: renesas: rzv2-evk-cn15-sd: Add ramp delay for SD0 regulator
  arm64: dts: renesas: rzt2h-n2h-evk: Add ramp delay for SD0 card regulator

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parents 22e6afdd 85c2601e

arch/arm64/boot/dts/renesas/r8a78000.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -698,7 +698,7 @@ scif0: serial@c0700000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0700000 0 0x40>;

			interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -708,7 +708,7 @@ scif1: serial@c0704000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0704000 0 0x40>;

			interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -718,7 +718,7 @@ scif3: serial@c0708000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0708000 0 0x40>;

			interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -728,7 +728,7 @@ scif4: serial@c070c000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc070c000 0 0x40>;

			interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -738,7 +738,7 @@ hscif0: serial@c0710000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc0710000 0 0x60>;

			interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -748,7 +748,7 @@ hscif1: serial@c0714000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc0714000 0 0x60>;

			interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -758,7 +758,7 @@ hscif2: serial@c0718000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc0718000 0 0x60>;

			interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -768,7 +768,7 @@ hscif3: serial@c071c000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc071c000 0 0x60>;

			interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";

arch/arm64/boot/dts/renesas/r9a09g057.dtsi

+0 −30
Original line number Diff line number Diff line
@@ -581,16 +581,6 @@ ostm7: timer@12c03000 { 
			status = "disabled";

		};



		wdt0: watchdog@11c00400 {

			compatible = "renesas,r9a09g057-wdt";

			reg = <0 0x11c00400 0 0x400>;

			clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;

			clock-names = "pclk", "oscclk";

			resets = <&cpg 0x75>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		wdt1: watchdog@14400000 {

			compatible = "renesas,r9a09g057-wdt";

			reg = <0 0x14400000 0 0x400>;
@@ -601,26 +591,6 @@ wdt1: watchdog@14400000 { 
			status = "disabled";

		};



		wdt2: watchdog@13000000 {

			compatible = "renesas,r9a09g057-wdt";

			reg = <0 0x13000000 0 0x400>;

			clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;

			clock-names = "pclk", "oscclk";

			resets = <&cpg 0x77>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		wdt3: watchdog@13000400 {

			compatible = "renesas,r9a09g057-wdt";

			reg = <0 0x13000400 0 0x400>;

			clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;

			clock-names = "pclk", "oscclk";

			resets = <&cpg 0x78>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		rtc: rtc@11c00800 {

			compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";

			reg = <0 0x11c00800 0 0x400>;

arch/arm64/boot/dts/renesas/r9a09g077.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -974,8 +974,8 @@ mii_conv3: mii-conv@3 { 


		cpg: clock-controller@80280000 {

			compatible = "renesas,r9a09g077-cpg-mssr";

			reg = <0 0x80280000 0 0x1000>,

			      <0 0x81280000 0 0x9000>;

			reg = <0 0x80280000 0 0x10000>,

			      <0 0x81280000 0 0x10000>;

			clocks = <&extal_clk>;

			clock-names = "extal";

			#clock-cells = <2>;

arch/arm64/boot/dts/renesas/r9a09g087.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -977,8 +977,8 @@ mii_conv3: mii-conv@3 { 


		cpg: clock-controller@80280000 {

			compatible = "renesas,r9a09g087-cpg-mssr";

			reg = <0 0x80280000 0 0x1000>,

			      <0 0x81280000 0 0x9000>;

			reg = <0 0x80280000 0 0x10000>,

			      <0 0x81280000 0 0x10000>;

			clocks = <&extal_clk>;

			clock-names = "extal";

			#clock-cells = <2>;

arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -162,7 +162,7 @@ versa3: clock-generator@68 { 
				       <100000000>;

		renesas,settings = [

		  80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27

		  00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86

		  00 40 00 00 00 00 00 00 06 0c 19 02 3b f0 90 86

		  a0 80 30 30 9c

		];

	};