Unverified Commit e4b2a0c2 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'sunxi-clk-fixes-for-6.16' of...

Merge tag 'sunxi-clk-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Pull Allwinner clock fixes from Chen-Yu Tsai:

 - Mark A523 MBUS clock as critical
 - Fix names of CSI related clocks on V3s
   This includes changes to the driver, DT bindings and DT files.
 - Fix parents of TCON clock on V3s

* tag 'sunxi-clk-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: v3s: Fix TCON clock parents
  clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
  clk: sunxi-ng: v3s: Fix CSI SCLK clock name
  clk: sunxi-ng: a523: Mark MBUS clock as critical
parents a42b4dcc 01fdcbc7
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+1 −1
Original line number Diff line number Diff line
@@ -110,7 +110,7 @@ examples:
        reg = <0x01cb4000 0x1000>;
        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_CSI>,
                 <&ccu CLK_CSI1_SCLK>,
                 <&ccu CLK_CSI_SCLK>,
                 <&ccu CLK_DRAM_CSI>;
        clock-names = "bus",
                      "mod",
+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ examples:
        reg = <0x01cb8000 0x1000>;
        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_CSI>,
             <&ccu CLK_CSI1_SCLK>,
             <&ccu CLK_CSI_SCLK>,
             <&ccu CLK_DRAM_CSI>;
        clock-names = "bus", "mod", "ram";
        resets = <&ccu RST_BUS_CSI>;
+1 −1
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ examples:
        reg = <0x01cb1000 0x1000>;
        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_CSI>,
                 <&ccu CLK_CSI1_SCLK>;
                 <&ccu CLK_CSI_SCLK>;
        clock-names = "bus", "mod";
        resets = <&ccu RST_BUS_CSI>;

+1 −1
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@@ -652,7 +652,7 @@ csi1: camera@1cb4000 {
			reg = <0x01cb4000 0x3000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_CSI>,
				 <&ccu CLK_CSI1_SCLK>,
				 <&ccu CLK_CSI_SCLK>,
				 <&ccu CLK_DRAM_CSI>;
			clock-names = "bus", "mod", "ram";
			resets = <&ccu RST_BUS_CSI>;
+2 −1
Original line number Diff line number Diff line
@@ -385,7 +385,8 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents,
					    0, 0,		/* no P */
					    24, 3,	/* mux */
					    BIT(31),	/* gate */
					    0, CCU_FEATURE_UPDATE_BIT);
					    CLK_IS_CRITICAL,
					    CCU_FEATURE_UPDATE_BIT);

static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw };

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