Unverified Commit e50db34e authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

RISC-V: Fix up some vector state related build failures 



I get a few build failures along the lines of

./arch/riscv/include/uapi/asm/sigcontext.h:19:36: error: field ‘v_state’ has incomplete type
   19 |         struct __riscv_v_ext_state v_state;
      |                                    ^~~~~~~
./arch/riscv/include/uapi/asm/sigcontext.h:32:49: error: field ‘sc_extdesc’ has incomplete type
   32 |                 struct __riscv_extra_ext_header sc_extdesc;

The V structures in question are defined for !assembly, so let's just do
so for the others.

Fixes: 8ee0b418 ("riscv: signal: Add sigcontext save/restore for vector")
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230619172101.18692-1-palmer@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent bcc87900

arch/riscv/include/uapi/asm/sigcontext.h

+4 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 
/* The size of END signal context header. */

#define END_HDR_SIZE	0x0



#ifndef __ASSEMBLY__



struct __sc_riscv_v_state {

	struct __riscv_v_ext_state v_state;

} __attribute__((aligned(16)));
@@ -33,4 +35,6 @@ struct sigcontext { 
	};

};



#endif /*!__ASSEMBLY__*/



#endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */