Commit e53ee4ac authored by Sai Krishna's avatar Sai Krishna Committed by Jakub Kicinski
Browse files

octeontx2-af: CN20k basic mbox operations and structures 



This patch adds basic mbox operation APIs and structures to add support
for mbox module on CN20k silicon. There are few CSR offsets, interrupts
changed between CN20k and prior Octeon series of devices.

Signed-off-by: default avatarSai Krishna <saikrishnag@marvell.com>
Signed-off-by: default avatarSunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarSubbaraya Sundeep <sbhatta@marvell.com>
Link: https://patch.msgid.link/1749639716-13868-3-git-send-email-sbhatta@marvell.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 25d51ebf

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -12,4 +12,4 @@ rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \ 
		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \

		  rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \

		  rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \

		  rvu_rep.o
 
		  rvu_rep.o cn20k/mbox_init.o

drivers/net/ethernet/marvell/octeontx2/af/cn20k/api.h

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/* SPDX-License-Identifier: GPL-2.0 */

/* Marvell RVU Admin Function driver

 *

 * Copyright (C) 2024 Marvell.

 *

 */



#ifndef CN20K_API_H

#define CN20K_API_H



#include "../rvu.h"



struct ng_rvu {

	struct mbox_ops         *rvu_mbox_ops;

	struct qmem             *pf_mbox_addr;

};



/* Mbox related APIs */

int cn20k_rvu_mbox_init(struct rvu *rvu, int type, int num);

int cn20k_rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,

			       int num, int type, unsigned long *pf_bmap);

void cn20k_free_mbox_memory(struct rvu *rvu);

#endif /* CN20K_API_H */

drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c

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// SPDX-License-Identifier: GPL-2.0

/* Marvell RVU Admin Function driver

 *

 * Copyright (C) 2024 Marvell.

 *

 */



#include <linux/interrupt.h>

#include <linux/irq.h>



#include "rvu_trace.h"

#include "mbox.h"

#include "reg.h"

#include "api.h"



int cn20k_rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,

			       int num, int type, unsigned long *pf_bmap)

{

	int region;

	u64 bar;



	for (region = 0; region < num; region++) {

		if (!test_bit(region, pf_bmap))

			continue;



		bar = (u64)phys_to_virt((u64)rvu->ng_rvu->pf_mbox_addr->base);

		bar += region * MBOX_SIZE;



		mbox_addr[region] = (void *)bar;



		if (!mbox_addr[region])

			return -ENOMEM;

	}

	return 0;

}



static int rvu_alloc_mbox_memory(struct rvu *rvu, int type,

				 int ndevs, int mbox_size)

{

	struct qmem *mbox_addr;

	dma_addr_t iova;

	int pf, err;



	/* Allocate contiguous memory for mailbox communication.

	 * eg: AF <=> PFx mbox memory

	 * This allocated memory is split into chunks of MBOX_SIZE

	 * and setup into each of the RVU PFs. In HW this memory will

	 * get aliased to an offset within BAR2 of those PFs.

	 *

	 * AF will access mbox memory using direct physical addresses

	 * and PFs will access the same shared memory from BAR2.

	 */



	err = qmem_alloc(rvu->dev, &mbox_addr, ndevs, mbox_size);

	if (err)

		return -ENOMEM;



	switch (type) {

	case TYPE_AFPF:

		rvu->ng_rvu->pf_mbox_addr = mbox_addr;

		iova = (u64)mbox_addr->iova;

		for (pf = 0; pf < ndevs; pf++) {

			rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFX_ADDR(pf),

				    (u64)iova);

			iova += mbox_size;

		}

		break;

	default:

		return 0;

	}



	return 0;

}



int cn20k_rvu_mbox_init(struct rvu *rvu, int type, int ndevs)

{

	int dev;



	if (!is_cn20k(rvu->pdev))

		return 0;



	for (dev = 0; dev < ndevs; dev++)

		rvu_write64(rvu, BLKADDR_RVUM,

			    RVU_MBOX_AF_PFX_CFG(dev), ilog2(MBOX_SIZE));



	return rvu_alloc_mbox_memory(rvu, type, ndevs, MBOX_SIZE);

}



void cn20k_free_mbox_memory(struct rvu *rvu)

{

	if (!is_cn20k(rvu->pdev))

		return;



	qmem_free(rvu->dev, rvu->ng_rvu->pf_mbox_addr);

}

drivers/net/ethernet/marvell/octeontx2/af/cn20k/reg.h

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/* SPDX-License-Identifier: GPL-2.0 */

/* Marvell RVU Admin Function driver

 *

 * Copyright (C) 2024 Marvell.

 *

 */



#ifndef RVU_MBOX_REG_H

#define RVU_MBOX_REG_H

#include "../rvu.h"

#include "../rvu_reg.h"



/* RVUM block registers */

#define RVU_PF_DISC				(0x0)

#define RVU_PRIV_PFX_DISC(a)			(0x8000208 | (a) << 16)

#define RVU_PRIV_HWVFX_DISC(a)			(0xD000000 | (a) << 12)



/* Mbox Registers */

/* RVU AF BAR0 Mbox registers for AF => PFx */

#define RVU_MBOX_AF_PFX_ADDR(a)			(0x5000 | (a) << 4)

#define RVU_MBOX_AF_PFX_CFG(a)			(0x6000 | (a) << 4)

#define RVU_AF_BAR2_SEL				(0x9000000)

#define RVU_AF_BAR2_PFID			(0x16400)

#define NIX_CINTX_INT_W1S(a)			(0xd30 | (a) << 12)

#define NIX_QINTX_CNT(a)			(0xc00 | (a) << 12)



#endif /* RVU_MBOX_REG_H */

drivers/net/ethernet/marvell/octeontx2/af/mbox.c

+3 −0
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@@ -10,8 +10,11 @@ 
#include <linux/pci.h>



#include "rvu_reg.h"

#include "cn20k/reg.h"

#include "cn20k/api.h"

#include "mbox.h"

#include "rvu_trace.h"

#include "rvu.h"



static const u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);