Commit e5abf748 authored by Martin K. Petersen's avatar Martin K. Petersen
Browse files

Merge patch series "ufs: host: mediatek: Provide features and fixes in MediaTek platforms" 

Peter Wang <peter.wang@mediatek.com> says:

This series fixes some defects and provide features in MediaTek UFS
drivers.

Link: https://lore.kernel.org/r/20240315083448.7185-1-peter.wang@mediatek.com


Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parents a86a3aa5 a6888d62

drivers/ufs/host/ufs-mediatek-sip.h

0 → 100644
+94 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2022 MediaTek Inc.

 */



#ifndef _UFS_MEDIATEK_SIP_H

#define _UFS_MEDIATEK_SIP_H



#include <linux/soc/mediatek/mtk_sip_svc.h>



/*

 * SiP (Slicon Partner) commands

 */

#define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)

#define UFS_MTK_SIP_VA09_PWR_CTRL         BIT(0)

#define UFS_MTK_SIP_DEVICE_RESET          BIT(1)

#define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)

#define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)

#define UFS_MTK_SIP_SRAM_PWR_CTRL         BIT(5)

#define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)

#define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)

#define UFS_MTK_SIP_MPHY_CTRL             BIT(8)

#define UFS_MTK_SIP_MTCMOS_CTRL           BIT(9)



/*

 * Multi-VCC by Numbering

 */

enum ufs_mtk_vcc_num {

	UFS_VCC_NONE = 0,

	UFS_VCC_1,

	UFS_VCC_2,

	UFS_VCC_MAX

};



enum ufs_mtk_mphy_op {

	UFS_MPHY_BACKUP = 0,

	UFS_MPHY_RESTORE

};



/*

 * SMC call wrapper function

 */

struct ufs_mtk_smc_arg {

	unsigned long cmd;

	struct arm_smccc_res *res;

	unsigned long v1;

	unsigned long v2;

	unsigned long v3;

	unsigned long v4;

	unsigned long v5;

	unsigned long v6;

	unsigned long v7;

};





static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)

{

	arm_smccc_smc(MTK_SIP_UFS_CONTROL,

		s.cmd,

		s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);

}



#define ufs_mtk_smc(...) \

	_ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})



/* Sip kernel interface */

#define ufs_mtk_va09_pwr_ctrl(res, on) \

	ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)



#define ufs_mtk_crypto_ctrl(res, enable) \

	ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)



#define ufs_mtk_ref_clk_notify(on, stage, res) \

	ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage)



#define ufs_mtk_device_reset_ctrl(high, res) \

	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)



#define ufs_mtk_sram_pwr_ctrl(on, res) \

	ufs_mtk_smc(UFS_MTK_SIP_SRAM_PWR_CTRL, &(res), on)



#define ufs_mtk_get_vcc_num(res) \

	ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))



#define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \

	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version)



#define ufs_mtk_mphy_ctrl(op, res) \

	ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op)



#define ufs_mtk_mtcmos_ctrl(op, res) \

	ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op)



#endif /* !_UFS_MEDIATEK_SIP_H */

drivers/ufs/host/ufs-mediatek.c

+115 −15
Original line number Diff line number Diff line
@@ -19,13 +19,14 @@ 
#include <linux/platform_device.h>

#include <linux/regulator/consumer.h>

#include <linux/reset.h>

#include <linux/soc/mediatek/mtk_sip_svc.h>



#include <ufs/ufshcd.h>

#include "ufshcd-pltfrm.h"

#include <ufs/ufs_quirks.h>

#include <ufs/unipro.h>



#include "ufs-mediatek.h"

#include "ufs-mediatek-sip.h"



static int  ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq);
@@ -118,6 +119,27 @@ static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba) 
	return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);

}



static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba)

{

	struct ufs_mtk_host *host = ufshcd_get_variant(hba);



	return (host->caps & UFS_MTK_CAP_TX_SKEW_FIX);

}



static bool ufs_mtk_is_rtff_mtcmos(struct ufs_hba *hba)

{

	struct ufs_mtk_host *host = ufshcd_get_variant(hba);



	return (host->caps & UFS_MTK_CAP_RTFF_MTCMOS);

}



static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)

{

	struct ufs_mtk_host *host = ufshcd_get_variant(hba);



	return (host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);

}



static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)

{

	u32 tmp;
@@ -169,16 +191,23 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba) 
static void ufs_mtk_host_reset(struct ufs_hba *hba)

{

	struct ufs_mtk_host *host = ufshcd_get_variant(hba);

	struct arm_smccc_res res;



	reset_control_assert(host->hci_reset);

	reset_control_assert(host->crypto_reset);

	reset_control_assert(host->unipro_reset);

	reset_control_assert(host->mphy_reset);



	usleep_range(100, 110);



	reset_control_deassert(host->unipro_reset);

	reset_control_deassert(host->crypto_reset);

	reset_control_deassert(host->hci_reset);

	reset_control_deassert(host->mphy_reset);



	/* restore mphy setting aftre mphy reset */

	if (host->mphy_reset)

		ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res);

}



static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
@@ -203,6 +232,8 @@ static void ufs_mtk_init_reset(struct ufs_hba *hba) 
				   "unipro_rst");

	ufs_mtk_init_reset_control(hba, &host->crypto_reset,

				   "crypto_rst");

	ufs_mtk_init_reset_control(hba, &host->mphy_reset,

				   "mphy_rst");

}



static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
@@ -622,6 +653,15 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba) 
	if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto"))

		host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO;



	if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))

		host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;



	if (of_property_read_bool(np, "mediatek,ufs-disable-mcq"))

		host->caps |= UFS_MTK_CAP_DISABLE_MCQ;



	if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos"))

		host->caps |= UFS_MTK_CAP_RTFF_MTCMOS;



	dev_info(hba->dev, "caps: 0x%x", host->caps);

}
@@ -885,6 +925,9 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba) 
	host->mcq_nr_intr = UFSHCD_MAX_Q_NR;

	pdev = container_of(hba->dev, struct platform_device, dev);



	if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)

		goto failed;



	for (i = 0; i < host->mcq_nr_intr; i++) {

		/* irq index 0 is legacy irq, sq/cq irq start from index 1 */

		irq = platform_get_irq(pdev, i + 1);
@@ -923,6 +966,7 @@ static int ufs_mtk_init(struct ufs_hba *hba) 
	struct ufs_mtk_host *host;

	struct Scsi_Host *shost = hba->host;

	int err = 0;

	struct arm_smccc_res res;



	host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);

	if (!host) {
@@ -951,6 +995,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) 


	ufs_mtk_init_reset(hba);



	/* backup mphy setting if mphy can reset */

	if (host->mphy_reset)

		ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res);



	/* Enable runtime autosuspend */

	hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
@@ -987,6 +1035,15 @@ static int ufs_mtk_init(struct ufs_hba *hba) 
	 * Enable phy clocks specifically here.

	 */

	ufs_mtk_mphy_power_on(hba, true);



	if (ufs_mtk_is_rtff_mtcmos(hba)) {

		/* First Restore here, to avoid backup unexpected value */

		ufs_mtk_mtcmos_ctrl(false, res);



		/* Power on to init */

		ufs_mtk_mtcmos_ctrl(true, res);

	}



	ufs_mtk_setup_clocks(hba, true, POST_CHANGE);



	host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
@@ -1303,26 +1360,36 @@ static void ufs_mtk_vsx_set_lpm(struct ufs_hba *hba, bool lpm) 


static void ufs_mtk_dev_vreg_set_lpm(struct ufs_hba *hba, bool lpm)

{

	if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)

		return;

	bool skip_vccqx = false;



	/* Skip if VCC is assumed always-on */

	if (!hba->vreg_info.vcc)

		return;



	/* Bypass LPM when device is still active */

	/* Prevent entering LPM when device is still active */

	if (lpm && ufshcd_is_ufs_dev_active(hba))

		return;



	/* Bypass LPM if VCC is enabled */

	if (lpm && hba->vreg_info.vcc->enabled)

		return;

	/* Skip vccqx lpm control and control vsx only */

	if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)

		skip_vccqx = true;



	/* VCC is always-on, control vsx only */

	if (!hba->vreg_info.vcc)

		skip_vccqx = true;



	/* Broken vcc keep vcc always on, most case control vsx only */

	if (lpm && hba->vreg_info.vcc && hba->vreg_info.vcc->enabled) {

		/* Some device vccqx/vsx can enter lpm */

		if (ufs_mtk_is_allow_vccqx_lpm(hba))

			skip_vccqx = false;

		else /* control vsx only */

			skip_vccqx = true;

	}



	if (lpm) {

		if (!skip_vccqx)

			ufs_mtk_vccqx_set_lpm(hba, lpm);

		ufs_mtk_vsx_set_lpm(hba, lpm);

	} else {

		ufs_mtk_vsx_set_lpm(hba, lpm);

		if (!skip_vccqx)

			ufs_mtk_vccqx_set_lpm(hba, lpm);

	}

}
@@ -1374,7 +1441,7 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 
	if (ufshcd_is_link_off(hba))

		ufs_mtk_device_reset_ctrl(0, res);



	ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, false, res);

	ufs_mtk_sram_pwr_ctrl(false, res);



	return 0;

fail:
@@ -1395,7 +1462,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 
	if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)

		ufs_mtk_dev_vreg_set_lpm(hba, false);



	ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, true, res);

	ufs_mtk_sram_pwr_ctrl(true, res);



	err = ufs_mtk_mphy_power_on(hba, true);

	if (err)
@@ -1438,6 +1505,17 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba) 
	if (mid == UFS_VENDOR_SAMSUNG) {

		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);

		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10);

	} else if (mid == UFS_VENDOR_MICRON) {

		/* Only for the host which have TX skew issue */

		if (ufs_mtk_is_tx_skew_fix(hba) &&

			(STR_PRFX_EQUAL("MT128GBCAV2U31", dev_info->model) ||

			STR_PRFX_EQUAL("MT256GBCAV4U31", dev_info->model) ||

			STR_PRFX_EQUAL("MT512GBCAV8U31", dev_info->model) ||

			STR_PRFX_EQUAL("MT256GBEAX4U40", dev_info->model) ||

			STR_PRFX_EQUAL("MT512GAYAX4U40", dev_info->model) ||

			STR_PRFX_EQUAL("MT001TAYAX8U40", dev_info->model))) {

			ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8);

		}

	}



	/*
@@ -1579,6 +1657,12 @@ static int ufs_mtk_clk_scale_notify(struct ufs_hba *hba, bool scale_up, 


static int ufs_mtk_get_hba_mac(struct ufs_hba *hba)

{

	struct ufs_mtk_host *host = ufshcd_get_variant(hba);



	/* MCQ operation not permitted */

	if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)

		return -EPERM;



	return MAX_SUPP_MAC;

}
@@ -1790,6 +1874,7 @@ static void ufs_mtk_remove(struct platform_device *pdev) 
static int ufs_mtk_system_suspend(struct device *dev)

{

	struct ufs_hba *hba = dev_get_drvdata(dev);

	struct arm_smccc_res res;

	int ret;



	ret = ufshcd_system_suspend(dev);
@@ -1798,15 +1883,22 @@ static int ufs_mtk_system_suspend(struct device *dev) 


	ufs_mtk_dev_vreg_set_lpm(hba, true);



	if (ufs_mtk_is_rtff_mtcmos(hba))

		ufs_mtk_mtcmos_ctrl(false, res);



	return 0;

}



static int ufs_mtk_system_resume(struct device *dev)

{

	struct ufs_hba *hba = dev_get_drvdata(dev);

	struct arm_smccc_res res;



	ufs_mtk_dev_vreg_set_lpm(hba, false);



	if (ufs_mtk_is_rtff_mtcmos(hba))

		ufs_mtk_mtcmos_ctrl(true, res);



	return ufshcd_system_resume(dev);

}

#endif
@@ -1815,6 +1907,7 @@ static int ufs_mtk_system_resume(struct device *dev) 
static int ufs_mtk_runtime_suspend(struct device *dev)

{

	struct ufs_hba *hba = dev_get_drvdata(dev);

	struct arm_smccc_res res;

	int ret = 0;



	ret = ufshcd_runtime_suspend(dev);
@@ -1823,12 +1916,19 @@ static int ufs_mtk_runtime_suspend(struct device *dev) 


	ufs_mtk_dev_vreg_set_lpm(hba, true);



	if (ufs_mtk_is_rtff_mtcmos(hba))

		ufs_mtk_mtcmos_ctrl(false, res);



	return 0;

}



static int ufs_mtk_runtime_resume(struct device *dev)

{

	struct ufs_hba *hba = dev_get_drvdata(dev);

	struct arm_smccc_res res;



	if (ufs_mtk_is_rtff_mtcmos(hba))

		ufs_mtk_mtcmos_ctrl(true, res);



	ufs_mtk_dev_vreg_set_lpm(hba, false);

drivers/ufs/host/ufs-mediatek.h

+11 −79
Original line number Diff line number Diff line
@@ -7,7 +7,6 @@ 
#define _UFS_MEDIATEK_H



#include <linux/bitops.h>

#include <linux/soc/mediatek/mtk_sip_svc.h>



/*

 * MCQ define and struct
@@ -99,18 +98,6 @@ enum { 
	VS_HIB_EXIT                 = 13,

};



/*

 * SiP commands

 */

#define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)

#define UFS_MTK_SIP_VA09_PWR_CTRL         BIT(0)

#define UFS_MTK_SIP_DEVICE_RESET          BIT(1)

#define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)

#define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)

#define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)

#define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)

#define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)



/*

 * VS_DEBUGCLOCKENABLE

 */
@@ -135,7 +122,17 @@ enum ufs_mtk_host_caps { 
	UFS_MTK_CAP_VA09_PWR_CTRL              = 1 << 1,

	UFS_MTK_CAP_DISABLE_AH8                = 1 << 2,

	UFS_MTK_CAP_BROKEN_VCC                 = 1 << 3,



	/*

	 * Override UFS_MTK_CAP_BROKEN_VCC's behavior to

	 * allow vccqx upstream to enter LPM

	 */

	UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,

	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,

	UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,

	UFS_MTK_CAP_DISABLE_MCQ                = 1 << 8,

	/* Control MTCMOS with RTFF */

	UFS_MTK_CAP_RTFF_MTCMOS                = 1 << 9,

};



struct ufs_mtk_crypt_cfg {
@@ -170,6 +167,7 @@ struct ufs_mtk_host { 
	struct reset_control *hci_reset;

	struct reset_control *unipro_reset;

	struct reset_control *crypto_reset;

	struct reset_control *mphy_reset;

	struct ufs_hba *hba;

	struct ufs_mtk_crypt_cfg *crypt;

	struct ufs_mtk_clk mclk;
@@ -191,70 +189,4 @@ struct ufs_mtk_host { 
/* MTK delay of autosuspend: 500 ms */

#define MTK_RPM_AUTOSUSPEND_DELAY_MS 500



/*

 * Multi-VCC by Numbering

 */

enum ufs_mtk_vcc_num {

	UFS_VCC_NONE = 0,

	UFS_VCC_1,

	UFS_VCC_2,

	UFS_VCC_MAX

};



/*

 * Host Power Control options

 */

enum {

	HOST_PWR_HCI = 0,

	HOST_PWR_MPHY

};



/*

 * SMC call wrapper function

 */

struct ufs_mtk_smc_arg {

	unsigned long cmd;

	struct arm_smccc_res *res;

	unsigned long v1;

	unsigned long v2;

	unsigned long v3;

	unsigned long v4;

	unsigned long v5;

	unsigned long v6;

	unsigned long v7;

};



static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)

{

	arm_smccc_smc(MTK_SIP_UFS_CONTROL,

		      s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);

}



#define ufs_mtk_smc(...) \

	_ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})



/*

 * SMC call interface

 */

#define ufs_mtk_va09_pwr_ctrl(res, on) \

	ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)



#define ufs_mtk_crypto_ctrl(res, enable) \

	ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)



#define ufs_mtk_ref_clk_notify(on, stage, res) \

	ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage)



#define ufs_mtk_device_reset_ctrl(high, res) \

	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)



#define ufs_mtk_host_pwr_ctrl(opt, on, res) \

	ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)



#define ufs_mtk_get_vcc_num(res) \

	ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))



#define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \

	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver)



#endif /* !_UFS_MEDIATEK_H */