Commit e69c2dd7 authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu/mes12: load unified mes fw on pipe0 and pipe1 



Enable unified mes firmware to load on pipe0 and pipe1.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f83cec3b

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+1 −1
Original line number Diff line number Diff line
@@ -1525,7 +1525,7 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe) 


	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix,

				       sizeof(ucode_prefix));

	if (adev->enable_uni_mes && pipe == AMDGPU_MES_SCHED_PIPE) {

	if (adev->enable_uni_mes) {

		snprintf(fw_name, sizeof(fw_name),

			 "amdgpu/%s_uni_mes.bin", ucode_prefix);

	} else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) &&

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

+3 −24
Original line number Diff line number Diff line
@@ -777,16 +777,11 @@ static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 
	if (enable) {

		data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);

		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,

		       (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0);

		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);

		WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);



		mutex_lock(&adev->srbm_mutex);

		for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

			if ((!adev->enable_mes_kiq || adev->enable_uni_mes) &&

			    pipe == AMDGPU_MES_KIQ_PIPE)

				continue;



			soc21_grbm_select(adev, 3, pipe, 0, 0);



			ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
@@ -800,8 +795,7 @@ static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 


		/* unhalt MES and activate pipe0 */

		data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);

		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,

		       (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0);

		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);

		WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);



		if (amdgpu_emu_mode)
@@ -817,8 +811,7 @@ static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 
		data = REG_SET_FIELD(data, CP_MES_CNTL,

				     MES_INVALIDATE_ICACHE, 1);

		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,

		       (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0);

		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);

		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);

		WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);

	}
@@ -833,10 +826,6 @@ static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 


	mutex_lock(&adev->srbm_mutex);

	for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

		if ((!adev->enable_mes_kiq || adev->enable_uni_mes) &&

		    pipe == AMDGPU_MES_KIQ_PIPE)

			continue;



		/* me=3, queue=0 */

		soc21_grbm_select(adev, 3, pipe, 0, 0);
@@ -1558,17 +1547,7 @@ static int mes_v12_0_early_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int pipe, r;



	if (adev->enable_uni_mes) {

		r = amdgpu_mes_init_microcode(adev, AMDGPU_MES_SCHED_PIPE);

		if (!r)

			return 0;



		adev->enable_uni_mes = false;

	}



	for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

		if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)

			continue;

		r = amdgpu_mes_init_microcode(adev, pipe);

		if (r)

			return r;