Commit eab7766c authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: Remove vram carveout support 



It is standing in the way of drm_gpuvm / VM_BIND support.  Not to
mention frequently broken and rarely tested.  And I think only needed
for a 10yr old not quite upstream SoC (msm8974).

Maybe we can add support back in later, but I'm doubtful.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Tested-by: default avatarAntonino Maniscalco <antomani103@gmail.com>
Reviewed-by: default avatarAntonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/661467/
parent 057e55f3

drivers/gpu/drm/msm/adreno/a2xx_gpu.c

+0 −8
Original line number Diff line number Diff line
@@ -551,14 +551,6 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) 
	else

		adreno_gpu->registers = a220_registers;



	if (!gpu->vm) {

		dev_err(dev->dev, "No memory protection without MMU\n");

		if (!allow_vram_carveout) {

			ret = -ENXIO;

			goto fail;

		}

	}



	return gpu;



fail:

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+0 −15
Original line number Diff line number Diff line
@@ -581,21 +581,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) 
			goto fail;

	}



	if (!gpu->vm) {

		/* TODO we think it is possible to configure the GPU to

		 * restrict access to VRAM carveout.  But the required

		 * registers are unknown.  For now just bail out and

		 * limp along with just modesetting.  If it turns out

		 * to not be possible to restrict access, then we must

		 * implement a cmdstream validator.

		 */

		DRM_DEV_ERROR(dev->dev, "No memory protection without IOMMU\n");

		if (!allow_vram_carveout) {

			ret = -ENXIO;

			goto fail;

		}

	}



	icc_path = devm_of_icc_get(&pdev->dev, "gfx-mem");

	if (IS_ERR(icc_path)) {

		ret = PTR_ERR(icc_path);

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+0 −15
Original line number Diff line number Diff line
@@ -695,21 +695,6 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) 


	adreno_gpu->uche_trap_base = 0xffff0000ffff0000ull;



	if (!gpu->vm) {

		/* TODO we think it is possible to configure the GPU to

		 * restrict access to VRAM carveout.  But the required

		 * registers are unknown.  For now just bail out and

		 * limp along with just modesetting.  If it turns out

		 * to not be possible to restrict access, then we must

		 * implement a cmdstream validator.

		 */

		DRM_DEV_ERROR(dev->dev, "No memory protection without IOMMU\n");

		if (!allow_vram_carveout) {

			ret = -ENXIO;

			goto fail;

		}

	}



	icc_path = devm_of_icc_get(&pdev->dev, "gfx-mem");

	if (IS_ERR(icc_path)) {

		ret = PTR_ERR(icc_path);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+1 −2
Original line number Diff line number Diff line
@@ -1786,7 +1786,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) 
		return ERR_PTR(ret);

	}



	if (gpu->vm)

	msm_mmu_set_fault_handler(gpu->vm->mmu, gpu, a5xx_fault_handler);



	/* Set up the preemption specific bits and pieces for each ringbuffer */

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+1 −2
Original line number Diff line number Diff line
@@ -2560,7 +2560,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 


	adreno_gpu->uche_trap_base = 0x1fffffffff000ull;



	if (gpu->vm)

	msm_mmu_set_fault_handler(gpu->vm->mmu, gpu, a6xx_fault_handler);



	a6xx_calc_ubwc_config(adreno_gpu);