Unverified Commit eb100397 authored by Yunhui Cui's avatar Yunhui Cui Committed by Alexandre Ghiti
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RISC-V: hwprobe: Expose Zicbom extension and its block size 



Expose Zicbom through hwprobe and also provide a key to extract its
respective block size.

[ alex: Fix merge conflicts and hwprobe numbering ]

Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Signed-off-by: default avatarYunhui Cui <cuiyunhui@bytedance.com>
Link: https://lore.kernel.org/r/20250226063206.71216-3-cuiyunhui@bytedance.com


Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
parent de70b532

Documentation/arch/riscv/hwprobe.rst

+6 −0
Original line number Diff line number Diff line
@@ -260,6 +260,9 @@ The following keys are defined: 
       defined in the RISC-V ISA manual starting from commit 4dc23d6229de

       ("Added Chapter title to BF16").



  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as

       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.
@@ -321,3 +324,6 @@ The following keys are defined: 
    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor

        extension is supported in the T-Head ISA extensions spec starting from

	commit a18c801634 ("Add T-Head VECTOR vendor extension. ").



* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which

  represents the size of the Zicbom block in bytes.

arch/riscv/include/asm/hwprobe.h

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


#include <uapi/asm/hwprobe.h>



#define RISCV_HWPROBE_MAX_KEY 11

#define RISCV_HWPROBE_MAX_KEY 12



static inline bool riscv_hwprobe_key_is_valid(__s64 key)

{

arch/riscv/include/uapi/asm/hwprobe.h

+2 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZFBFMIN	(1ULL << 52)

#define		RISCV_HWPROBE_EXT_ZVFBFMIN	(1ULL << 53)

#define		RISCV_HWPROBE_EXT_ZVFBFWMA	(1ULL << 54)

#define		RISCV_HWPROBE_EXT_ZICBOM	(1ULL << 55)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
@@ -100,6 +101,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_MISALIGNED_VECTOR_FAST		3

#define		RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED	4

#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0	11

#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE	12

/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */



/* Flags */

arch/riscv/kernel/sys_hwprobe.c

+7 −1
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZCA);

		EXT_KEY(ZCB);

		EXT_KEY(ZCMOP);

		EXT_KEY(ZICBOM);

		EXT_KEY(ZICBOZ);

		EXT_KEY(ZICNTR);

		EXT_KEY(ZICOND);
@@ -166,7 +167,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
	pair->value &= ~missing;

}



static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext)

static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext)

{

	struct riscv_hwprobe pair;
@@ -284,6 +285,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, 
		if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))

			pair->value = riscv_cboz_block_size;

		break;

	case RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE:

		pair->value = 0;

		if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))

			pair->value = riscv_cbom_block_size;

		break;

	case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:

		pair->value = user_max_virt_addr();

		break;