Commit ec0c7afa authored by Ankit Nautiyal's avatar Ankit Nautiyal Committed by Jani Nikula
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drm/i915/display: Add macro for checking 3 DSC engines 



3 DSC engines per pipe is currently supported only for BMG.
Add a macro to check whether a platform supports 3 DSC engines per pipe.

v2:Fix Typo in macro argument. (Suraj).
Added fixes tag.

Bspec: 50175
Fixes: be7f5fcd ("drm/i915/dp: Enable 3 DSC engines for 12 slices")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: <stable@vger.kernel.org> # v6.14+
Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250414085701.2802374-1-ankit.k.nautiyal@intel.com


(cherry picked from commit 6998cfce)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 8ffd015d

drivers/gpu/drm/i915/display/intel_display_device.h

+1 −0
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ struct intel_display_platforms { 
#define HAS_DPT(__display)		(DISPLAY_VER(__display) >= 13)

#define HAS_DSB(__display)		(DISPLAY_INFO(__display)->has_dsb)

#define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)

#define HAS_DSC_3ENGINES(__display)	(DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))

#define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))

#define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)

#define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)