Commit ef15f683 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'samsung-pinctrl-6.13' of... 

Merge tag 'samsung-pinctrl-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung

 into devel

Samsung pinctrl drivers changes for v6.13

1. Add new pin controller drivers for new Samsung SoCs: Exynos8895,
   Exynos9810, Exynos990.

2. Correct the condition when applying further interrupt constraints on
   certain Samsung pin controllers.  The condition was simply not
   effective.

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents c34b2062 6d2dbd4c

Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml

+15 −8
Original line number Diff line number Diff line
@@ -42,10 +42,13 @@ properties: 
              - samsung,exynos5433-wakeup-eint

              - samsung,exynos7885-wakeup-eint

              - samsung,exynos850-wakeup-eint

              - samsung,exynos8895-wakeup-eint

          - const: samsung,exynos7-wakeup-eint

      - items:

          - enum:

              - google,gs101-wakeup-eint

              - samsung,exynos9810-wakeup-eint

              - samsung,exynos990-wakeup-eint

              - samsung,exynosautov9-wakeup-eint

          - const: samsung,exynos850-wakeup-eint

          - const: samsung,exynos7-wakeup-eint
@@ -91,14 +94,18 @@ allOf: 
  - if:

      properties:

        compatible:

          oneOf:

            # Match without "contains", to skip newer variants which are still

            # compatible with samsung,exynos7-wakeup-eint

          enum:

            - samsung,s5pv210-wakeup-eint

            - enum:

                - samsung,exynos4210-wakeup-eint

            - samsung,exynos5433-wakeup-eint

                - samsung,exynos7-wakeup-eint

                - samsung,s5pv210-wakeup-eint

            - contains:

                enum:

                  - samsung,exynos5433-wakeup-eint

                  - samsung,exynos7885-wakeup-eint

                  - samsung,exynos8895-wakeup-eint

    then:

      properties:

        interrupts:

Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml

+3 −0
Original line number Diff line number Diff line
@@ -53,6 +53,9 @@ properties: 
      - samsung,exynos7-pinctrl

      - samsung,exynos7885-pinctrl

      - samsung,exynos850-pinctrl

      - samsung,exynos8895-pinctrl

      - samsung,exynos9810-pinctrl

      - samsung,exynos990-pinctrl

      - samsung,exynosautov9-pinctrl

      - samsung,exynosautov920-pinctrl

      - tesla,fsd-pinctrl

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

+431 −0
Original line number Diff line number Diff line
@@ -58,6 +58,15 @@ static const struct samsung_pin_bank_type exynos850_bank_type_alive = { 
	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

};



/*

 * Bank type for non-alive type. Bit fields:

 * CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2

 */

static const struct samsung_pin_bank_type exynos8895_bank_type_off  = {

	.fld_width = { 4, 1, 2, 3, 2, 2, },

	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },

};



/* Pad retention control code for accessing PMU regmap */

static atomic_t exynos_shared_retention_refcnt;
@@ -618,6 +627,300 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { 
	.num_ctrl	= ARRAY_SIZE(exynos850_pin_ctrl),

};



/* pin banks of exynos990 pin-controller 0 (ALIVE) */

static struct samsung_pin_bank_data exynos990_pin_banks0[] = {

	/* Must start with EINTG banks, ordered by EINT group number. */

	EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),

	EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),

	EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),

	EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),

	EXYNOS850_PIN_BANK_EINTW(2, 0x080, "gpa4", 0x10),

	EXYNOS850_PIN_BANK_EINTN(7, 0x0A0, "gpq0"),

};



/* pin banks of exynos990 pin-controller 1 (CMGP) */

static struct samsung_pin_bank_data exynos990_pin_banks1[] = {

	/* Must start with EINTG banks, ordered by EINT group number. */

	EXYNOS850_PIN_BANK_EINTN(1, 0x000, "gpm0"),

	EXYNOS850_PIN_BANK_EINTN(1, 0x020, "gpm1"),

	EXYNOS850_PIN_BANK_EINTN(1, 0x040, "gpm2"),

	EXYNOS850_PIN_BANK_EINTN(1, 0x060, "gpm3"),

	EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x00),

	EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x04),

	EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x08),

	EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x0c),

	EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x10),

	EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x14),

	EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x18),

	EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x1c),

	EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x20),

	EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x24),

	EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x28),

	EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x2c),

	EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x30),

	EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x34),

	EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x38),

	EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x3c),

	EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x40),

	EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x44),

	EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x48),

	EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x4c),

	EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x50),

	EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x54),

	EXYNOS850_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x58),

	EXYNOS850_PIN_BANK_EINTW(1, 0x360, "gpm27", 0x5c),

	EXYNOS850_PIN_BANK_EINTW(1, 0x380, "gpm28", 0x60),

	EXYNOS850_PIN_BANK_EINTW(1, 0x3A0, "gpm29", 0x64),

	EXYNOS850_PIN_BANK_EINTW(1, 0x3C0, "gpm30", 0x68),

	EXYNOS850_PIN_BANK_EINTW(1, 0x3E0, "gpm31", 0x6c),

	EXYNOS850_PIN_BANK_EINTW(1, 0x400, "gpm32", 0x70),

	EXYNOS850_PIN_BANK_EINTW(1, 0x420, "gpm33", 0x74),



};



/* pin banks of exynos990 pin-controller 2 (HSI1) */

static struct samsung_pin_bank_data exynos990_pin_banks2[] = {

	/* Must start with EINTG banks, ordered by EINT group number. */

	EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),

	EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04),

	EXYNOS850_PIN_BANK_EINTG(3, 0x040, "gpf2", 0x08),

};



/* pin banks of exynos990 pin-controller 3 (HSI2) */

static struct samsung_pin_bank_data exynos990_pin_banks3[] = {

	/* Must start with EINTG banks, ordered by EINT group number. */

	EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf3", 0x00),

};



/* pin banks of exynos990 pin-controller 4 (PERIC0) */

static struct samsung_pin_bank_data exynos990_pin_banks4[] = {

	/* Must start with EINTG banks, ordered by EINT group number. */

	EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00),

	EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04),

	EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08),

	EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp3", 0x0C),

	EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp4", 0x10),

	EXYNOS850_PIN_BANK_EINTG(2, 0x0A0, "gpg0", 0x14),

};



/* pin banks of exynos990 pin-controller 5 (PERIC1) */

static struct samsung_pin_bank_data exynos990_pin_banks5[] = {

	/* Must start with EINTG banks, ordered by EINT group number. */

	EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp5", 0x00),

	EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp6", 0x04),

	EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp7", 0x08),

	EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp8", 0x0C),

	EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp9", 0x10),

	EXYNOS850_PIN_BANK_EINTG(6, 0x0A0, "gpc0", 0x14),

	EXYNOS850_PIN_BANK_EINTG(4, 0x0C0, "gpg1", 0x18),

	EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpb0", 0x1C),

	EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb1", 0x20),

	EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb2", 0x24),

};



/* pin banks of exynos990 pin-controller 6 (VTS) */

static struct samsung_pin_bank_data exynos990_pin_banks6[] = {

	/* Must start with EINTG banks, ordered by EINT group number. */

	EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpv0", 0x00),

};



static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = {

	{

		/* pin-controller instance 0 ALIVE data */

		.pin_banks	= exynos990_pin_banks0,

		.nr_banks	= ARRAY_SIZE(exynos990_pin_banks0),

		.eint_wkup_init = exynos_eint_wkup_init,

	}, {

		/* pin-controller instance 1 CMGP data */

		.pin_banks	= exynos990_pin_banks1,

		.nr_banks	= ARRAY_SIZE(exynos990_pin_banks1),

		.eint_wkup_init = exynos_eint_wkup_init,

	}, {

		/* pin-controller instance 2 HSI1 data */

		.pin_banks	= exynos990_pin_banks2,

		.nr_banks	= ARRAY_SIZE(exynos990_pin_banks2),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 3 HSI2 data */

		.pin_banks	= exynos990_pin_banks3,

		.nr_banks	= ARRAY_SIZE(exynos990_pin_banks3),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 4 PERIC0 data */

		.pin_banks	= exynos990_pin_banks4,

		.nr_banks	= ARRAY_SIZE(exynos990_pin_banks4),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 5 PERIC1 data */

		.pin_banks	= exynos990_pin_banks5,

		.nr_banks	= ARRAY_SIZE(exynos990_pin_banks5),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 6 VTS data */

		.pin_banks	= exynos990_pin_banks6,

		.nr_banks	= ARRAY_SIZE(exynos990_pin_banks6),

	},

};



const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = {

	.ctrl		= exynos990_pin_ctrl,

	.num_ctrl	= ARRAY_SIZE(exynos990_pin_ctrl),

};



/* pin banks of exynos9810 pin-controller 0 (ALIVE) */

static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = {

	EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"),

	EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00),

	EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04),

	EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08),

	EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c),

	EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"),

	EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10),

};



/* pin banks of exynos9810 pin-controller 1 (AUD) */

static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = {

	EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),

	EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04),

	EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08),

};



/* pin banks of exynos9810 pin-controller 2 (CHUB) */

static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = {

	EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00),

	EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04),

};



/* pin banks of exynos9810 pin-controller 3 (CMGP) */

static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = {

	EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),

	EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),

	EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),

	EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C),

	EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),

	EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14),

	EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18),

	EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C),

	EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20),

	EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24),

	EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28),

	EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C),

	EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30),

	EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34),

	EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38),

	EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C),

	EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40),

	EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44),

	EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48),

	EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C),

};



/* pin banks of exynos9810 pin-controller 4 (FSYS0) */

static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = {

	EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00),

};



/* pin banks of exynos9810 pin-controller 5 (FSYS1) */

static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = {

	EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00),

	EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04),

};



/* pin banks of exynos9810 pin-controller 6 (PERIC0) */

static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = {

	EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00),

	EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04),

	EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08),

	EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C),

	EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),

	EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),

	EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18),

};



/* pin banks of exynos9810 pin-controller 7 (PERIC1) */

static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = {

	EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00),

	EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04),

	EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08),

	EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C),

	EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10),

	EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),

	EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18),

};



/* pin banks of exynos9810 pin-controller 8 (VTS) */

static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = {

	EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00),

};



static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = {

	{

		/* pin-controller instance 0 ALIVE data */

		.pin_banks      = exynos9810_pin_banks0,

		.nr_banks       = ARRAY_SIZE(exynos9810_pin_banks0),

		.eint_wkup_init = exynos_eint_wkup_init,

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend        = exynos_pinctrl_suspend,

		.resume         = exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 1 AUD data */

		.pin_banks      = exynos9810_pin_banks1,

		.nr_banks       = ARRAY_SIZE(exynos9810_pin_banks1),

	}, {

		/* pin-controller instance 2 CHUB data */

		.pin_banks      = exynos9810_pin_banks2,

		.nr_banks       = ARRAY_SIZE(exynos9810_pin_banks2),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend        = exynos_pinctrl_suspend,

		.resume         = exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 3 CMGP data */

		.pin_banks      = exynos9810_pin_banks3,

		.nr_banks       = ARRAY_SIZE(exynos9810_pin_banks3),

		.eint_wkup_init = exynos_eint_wkup_init,

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend        = exynos_pinctrl_suspend,

		.resume         = exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 4 FSYS0 data */

		.pin_banks      = exynos9810_pin_banks4,

		.nr_banks       = ARRAY_SIZE(exynos9810_pin_banks4),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend        = exynos_pinctrl_suspend,

		.resume         = exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 5 FSYS1 data */

		.pin_banks      = exynos9810_pin_banks5,

		.nr_banks       = ARRAY_SIZE(exynos9810_pin_banks5),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend        = exynos_pinctrl_suspend,

		.resume         = exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 6 PERIC0 data */

		.pin_banks      = exynos9810_pin_banks6,

		.nr_banks       = ARRAY_SIZE(exynos9810_pin_banks6),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend        = exynos_pinctrl_suspend,

		.resume         = exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 7 PERIC1 data */

		.pin_banks      = exynos9810_pin_banks7,

		.nr_banks       = ARRAY_SIZE(exynos9810_pin_banks7),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend        = exynos_pinctrl_suspend,

		.resume         = exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 8 VTS data */

		.pin_banks      = exynos9810_pin_banks8,

		.nr_banks       = ARRAY_SIZE(exynos9810_pin_banks8),

	},

};



const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = {

	.ctrl		= exynos9810_pin_ctrl,

	.num_ctrl	= ARRAY_SIZE(exynos9810_pin_ctrl),

};



/* pin banks of exynosautov9 pin-controller 0 (ALIVE) */

static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = {

	EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
@@ -866,6 +1169,134 @@ const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = 
	.num_ctrl	= ARRAY_SIZE(exynosautov920_pin_ctrl),

};



/* pin banks of exynos8895 pin-controller 0 (ALIVE) */

static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = {

	EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00),

	EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04),

	EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08),

	EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c),

	EXYNOS_PIN_BANK_EINTW(7, 0x0a0, "gpa4", 0x24),

};



/* pin banks of exynos8895 pin-controller 1 (ABOX) */

static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00),

	EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04),

	EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08),

};



/* pin banks of exynos8895 pin-controller 2 (VTS) */

static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00),

};



/* pin banks of exynos8895 pin-controller 3 (FSYS0) */

static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = {

	EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00),

	EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04),

};



/* pin banks of exynos8895 pin-controller 4 (FSYS1) */

static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00),

	EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04),

};



/* pin banks of exynos8895 pin-controller 5 (BUSC) */

static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00),

};



/* pin banks of exynos8895 pin-controller 6 (PERIC0) */

static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00),

	EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04),

	EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08),

	EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C),

	EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),

	EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpe7", 0x14),

	EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf1", 0x18),

};



/* pin banks of exynos8895 pin-controller 7 (PERIC1) */

static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00),

	EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04),

	EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08),

	EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C),

	EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),

	EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpk0", 0x14),

	EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpe5", 0x18),

	EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C),

	EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20),

	EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24),

	EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28),

	EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C),

	EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30),

	EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),

};



static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = {

	{

		/* pin-controller instance 0 ALIVE data */

		.pin_banks	= exynos8895_pin_banks0,

		.nr_banks	= ARRAY_SIZE(exynos8895_pin_banks0),

		.eint_gpio_init = exynos_eint_gpio_init,

		.eint_wkup_init = exynos_eint_wkup_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 1 ABOX data */

		.pin_banks	= exynos8895_pin_banks1,

		.nr_banks	= ARRAY_SIZE(exynos8895_pin_banks1),

	}, {

		/* pin-controller instance 2 VTS data */

		.pin_banks	= exynos8895_pin_banks2,

		.nr_banks	= ARRAY_SIZE(exynos8895_pin_banks2),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 3 FSYS0 data */

		.pin_banks	= exynos8895_pin_banks3,

		.nr_banks	= ARRAY_SIZE(exynos8895_pin_banks3),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 4 FSYS1 data */

		.pin_banks	= exynos8895_pin_banks4,

		.nr_banks	= ARRAY_SIZE(exynos8895_pin_banks4),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 5 BUSC data */

		.pin_banks	= exynos8895_pin_banks5,

		.nr_banks	= ARRAY_SIZE(exynos8895_pin_banks5),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 6 PERIC0 data */

		.pin_banks	= exynos8895_pin_banks6,

		.nr_banks	= ARRAY_SIZE(exynos8895_pin_banks6),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 7 PERIC1 data */

		.pin_banks	= exynos8895_pin_banks7,

		.nr_banks	= ARRAY_SIZE(exynos8895_pin_banks7),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	},

};



const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = {

	.ctrl		= exynos8895_pin_ctrl,

	.num_ctrl	= ARRAY_SIZE(exynos8895_pin_ctrl),

};



/*

 * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three

 * gpio/pin-mux/pinconfig controllers.

drivers/pinctrl/samsung/pinctrl-exynos.h

+10 −0
Original line number Diff line number Diff line
@@ -141,6 +141,16 @@ 
		.name		= id				\

	}



#define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs)		\

	{							\

		.type		= &exynos8895_bank_type_off,	\

		.pctl_offset	= reg,				\

		.nr_pins	= pins,				\

		.eint_type	= EINT_TYPE_GPIO,		\

		.eint_offset	= offs,				\

		.name		= id				\

	}



#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs)	\

	{							\

		.type			= &exynos850_bank_type_off,	\

drivers/pinctrl/samsung/pinctrl-samsung.c

+6 −0
Original line number Diff line number Diff line
@@ -1477,6 +1477,12 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { 
		.data = &exynos7885_of_data },

	{ .compatible = "samsung,exynos850-pinctrl",

		.data = &exynos850_of_data },

	{ .compatible = "samsung,exynos8895-pinctrl",

		.data = &exynos8895_of_data },

	{ .compatible = "samsung,exynos9810-pinctrl",

		.data = &exynos9810_of_data },

	{ .compatible = "samsung,exynos990-pinctrl",

		.data = &exynos990_of_data },

	{ .compatible = "samsung,exynosautov9-pinctrl",

		.data = &exynosautov9_of_data },

	{ .compatible = "samsung,exynosautov920-pinctrl",