Commit efbacd8a authored by Yang Wang's avatar Yang Wang Committed by Alex Deucher
Browse files

drm/amd/pm: unified smu feature cap interface 



add a unified interface to provide smu feature cap set.

Signed-off-by: default avatarYang Wang <kevinyang.wang@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 10a9c09a

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+29 −0
Original line number Diff line number Diff line
@@ -1315,6 +1315,33 @@ static void smu_init_power_profile(struct smu_context *smu) 
	smu_power_profile_mode_get(smu, smu->power_profile_mode);

}



void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id)

{

	struct smu_feature_cap *fea_cap = &smu->fea_cap;



	if (fea_id >= SMU_FEATURE_CAP_ID__COUNT)

		return;



	set_bit(fea_id, fea_cap->cap_map);

}



bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id)

{

	struct smu_feature_cap *fea_cap = &smu->fea_cap;



	if (fea_id >= SMU_FEATURE_CAP_ID__COUNT)

		return false;



	return test_bit(fea_id, fea_cap->cap_map);

}



static void smu_feature_cap_init(struct smu_context *smu)

{

	struct smu_feature_cap *fea_cap = &smu->fea_cap;



	bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT);

}



static int smu_sw_init(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = ip_block->adev;
@@ -1347,6 +1374,8 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block) 
	INIT_DELAYED_WORK(&smu->swctf_delayed_work,

			  smu_swctf_delayed_work_handler);



	smu_feature_cap_init(smu);



	ret = smu_smc_table_sw_init(smu);

	if (ret) {

		dev_err(adev->dev, "Failed to sw init smc table!\n");

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+12 −0
Original line number Diff line number Diff line
@@ -528,6 +528,14 @@ enum smu_fw_status { 
 */

#define SMU_WBRF_EVENT_HANDLING_PACE	10



enum smu_feature_cap_id {

	SMU_FEATURE_CAP_ID__COUNT,

};



struct smu_feature_cap {

	DECLARE_BITMAP(cap_map, SMU_FEATURE_CAP_ID__COUNT);

};



struct smu_context {

	struct amdgpu_device            *adev;

	struct amdgpu_irq_src		irq_source;
@@ -550,6 +558,7 @@ struct smu_context { 
	struct amd_pp_display_configuration  *display_config;

	struct smu_baco_context		smu_baco;

	struct smu_temperature_range	thermal_range;

	struct smu_feature_cap		fea_cap;

	void *od_settings;



	struct smu_umd_pstate_table	pstate_table;
@@ -1788,4 +1797,7 @@ ssize_t smu_get_pm_policy_info(struct smu_context *smu, 
			       enum pp_pm_policy p_type, char *sysbuf);



#endif



void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id);

bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id);

#endif