Commit f09ed834 authored by Cosmin Ratiu's avatar Cosmin Ratiu Committed by Leon Romanovsky
Browse files

net/mlx5: qos: Add ifc support for cross-esw scheduling 



This adds the capability bit and the vport element fields related to
cross-esw scheduling.

Signed-off-by: default avatarCosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20241204220931.254964-5-tariqt@nvidia.com


Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent 03713108

include/linux/mlx5/mlx5_ifc.h

+8 −3
Original line number Diff line number Diff line
@@ -1095,7 +1095,9 @@ struct mlx5_ifc_qos_cap_bits { 
	u8         log_esw_max_sched_depth[0x4];

	u8         reserved_at_10[0x10];



	u8         reserved_at_20[0xb];

	u8         reserved_at_20[0x9];

	u8         esw_cross_esw_sched[0x1];

	u8         reserved_at_2a[0x1];

	u8         log_max_qos_nic_queue_group[0x5];

	u8         reserved_at_30[0x10];
@@ -4139,13 +4141,16 @@ struct mlx5_ifc_tsar_element_bits { 
};



struct mlx5_ifc_vport_element_bits {

	u8         reserved_at_0[0x10];

	u8         reserved_at_0[0x4];

	u8         eswitch_owner_vhca_id_valid[0x1];

	u8         eswitch_owner_vhca_id[0xb];

	u8         vport_number[0x10];

};



struct mlx5_ifc_vport_tc_element_bits {

	u8         traffic_class[0x4];

	u8         reserved_at_4[0xc];

	u8         eswitch_owner_vhca_id_valid[0x1];

	u8         eswitch_owner_vhca_id[0xb];

	u8         vport_number[0x10];

};