Unverified Commit f0c9363d authored by Mayuresh Chitale's avatar Mayuresh Chitale Committed by Palmer Dabbelt
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perf/riscv-sbi: Add platform specific firmware event handling 



The SBI v2.0 specification pointed to by the link below reserves the
event code 0xffff for platform specific firmware events. Update the driver
to be able to parse and program such events. The platform specific
firmware events must now be specified in the perf command as below:
perf stat -e rCxxx ...
where bits[63:62] = 0x3 of the event config indicate a platform specific
firmware event and xxx indicate the actual event code which is passed
as the event data.

Signed-off-by: default avatarMayuresh Chitale <mchitale@ventanamicro.com>
Link: https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v2.0/riscv-sbi.pdf
Link: https://lore.kernel.org/r/20240812051109.6496-1-mchitale@ventanamicro.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 47b9533c

arch/riscv/include/asm/sbi.h

+1 −0
Original line number Diff line number Diff line
@@ -158,6 +158,7 @@ struct riscv_pmu_snapshot_data { 


#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)

#define RISCV_PMU_RAW_EVENT_IDX 0x20000

#define RISCV_PLAT_FW_EVENT	0xFFFF



/** General pmu event codes specified in SBI PMU extension */

enum sbi_pmu_hw_generic_events_t {

drivers/perf/riscv_pmu_sbi.c

+22 −9
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ asm volatile(ALTERNATIVE( \ 
#define PERF_EVENT_FLAG_LEGACY		BIT(SYSCTL_LEGACY)



PMU_FORMAT_ATTR(event, "config:0-47");

PMU_FORMAT_ATTR(firmware, "config:63");

PMU_FORMAT_ATTR(firmware, "config:62-63");



static bool sbi_v2_available;

static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available);
@@ -507,7 +507,6 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) 
{

	u32 type = event->attr.type;

	u64 config = event->attr.config;

	int bSoftware;

	u64 raw_config_val;

	int ret;
@@ -528,18 +527,32 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) 
		break;

	case PERF_TYPE_RAW:

		/*

		 * As per SBI specification, the upper 16 bits must be unused for

		 * a raw event. Use the MSB (63b) to distinguish between hardware

		 * raw event and firmware events.

		 * As per SBI specification, the upper 16 bits must be unused

		 * for a raw event.

		 * Bits 63:62 are used to distinguish between raw events

		 * 00 - Hardware raw event

		 * 10 - SBI firmware events

		 * 11 - Risc-V platform specific firmware event

		 */

		bSoftware = config >> 63;

		raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;

		if (bSoftware) {

		switch (config >> 62) {

		case 0:

			ret = RISCV_PMU_RAW_EVENT_IDX;

			*econfig = raw_config_val;

			break;

		case 2:

			ret = (raw_config_val & 0xFFFF) |

				(SBI_PMU_EVENT_TYPE_FW << 16);

		} else {

			ret = RISCV_PMU_RAW_EVENT_IDX;

			break;

		case 3:

			/*

			 * For Risc-V platform specific firmware events

			 * Event code - 0xFFFF

			 * Event data - raw event encoding

			 */

			ret = SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT;

			*econfig = raw_config_val;

			break;

		}

		break;

	default: