Commit f0cb3463 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
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clk: renesas: r9a08g045: Add MSTOP for GPIO 



The GPIO module also supports MSTOP. Add it in the description of the gpio
clock.

Fixes: c4969595 ("clk: renesas: r9a08g045: Drop power domain instantiation")
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806092129.621194-2-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 45bf4bff

drivers/clk/renesas/r9a08g045-cpg.c

+2 −1
Original line number Diff line number Diff line
@@ -285,7 +285,8 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { 
					MSTOP(BUS_MCPU2, BIT(5))),

	DEF_MOD("scif5_clk_pck",	R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5,

					MSTOP(BUS_MCPU3, BIT(4))),

	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, 0),

	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0,

					MSTOP(BUS_PERI_CPU, BIT(6))),

	DEF_MOD("adc_adclk",		R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0,

					MSTOP(BUS_MCPU2, BIT(14))),

	DEF_MOD("adc_pclk",		R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1,