Commit f1e5a666 authored by Yinjie Yao's avatar Yinjie Yao Committed by Alex Deucher
Browse files

drm/amdgpu/vcn: set no_user_fence for VCN v3.0 enc/dec rings 



VCN encoder and decoder rings do not support 64-bit user fence writes,
reject CS submissions with user fences.

Fixes: cf14826c ("drm/amdgpu: add VCN3.0 support for Sienna_Cichlid")
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarYinjie Yao <yinjie.yao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 663bed3c7b8b9a7624b0d95d300ddae034ad0614)
parent 4f317863

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+3 −0
Original line number Diff line number Diff line
@@ -1856,6 +1856,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 
	.type = AMDGPU_RING_TYPE_VCN_DEC,

	.align_mask = 0x3f,

	.nop = VCN_DEC_SW_CMD_NO_OP,

	.no_user_fence = true,

	.secure_submission_supported = true,

	.get_rptr = vcn_v3_0_dec_ring_get_rptr,

	.get_wptr = vcn_v3_0_dec_ring_get_wptr,
@@ -2036,6 +2037,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 
static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {

	.type = AMDGPU_RING_TYPE_VCN_DEC,

	.align_mask = 0xf,

	.no_user_fence = true,

	.secure_submission_supported = true,

	.get_rptr = vcn_v3_0_dec_ring_get_rptr,

	.get_wptr = vcn_v3_0_dec_ring_get_wptr,
@@ -2138,6 +2140,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 
	.type = AMDGPU_RING_TYPE_VCN_ENC,

	.align_mask = 0x3f,

	.nop = VCN_ENC_CMD_NO_OP,

	.no_user_fence = true,

	.get_rptr = vcn_v3_0_enc_ring_get_rptr,

	.get_wptr = vcn_v3_0_enc_ring_get_wptr,

	.set_wptr = vcn_v3_0_enc_ring_set_wptr,