Commit f3dc9246 authored by Matthew Auld's avatar Matthew Auld
Browse files

drm/xe/migrate: fix pat index usage 



XE_CACHE_WB must be converted into the per-platform pat index for that
particular caching mode, otherwise we are just encoding whatever happens
to be the value of that enum.

Fixes: e8babb28 ("drm/xe: Convert multiple bind ops into single job")
Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
Reviewed-by: default avatarNirmoy Das <nirmoy.das@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241126181259.159713-3-matthew.auld@intel.com
parent f8c91d96

drivers/gpu/drm/xe/xe_migrate.c

+2 −1
Original line number Diff line number Diff line
@@ -1350,6 +1350,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m, 


	/* For sysmem PTE's, need to map them in our hole.. */

	if (!IS_DGFX(xe)) {

		u16 pat_index = xe->pat.idx[XE_CACHE_WB];

		u32 ptes, ofs;



		ppgtt_ofs = NUM_KERNEL_PDE - 1;
@@ -1409,7 +1410,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m, 
						pt_bo->update_index = current_update;



					addr = vm->pt_ops->pte_encode_bo(pt_bo, 0,

									 XE_CACHE_WB, 0);

									 pat_index, 0);

					bb->cs[bb->len++] = lower_32_bits(addr);

					bb->cs[bb->len++] = upper_32_bits(addr);

				}