Commit f8078d51 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch kvm-arm64/vgic-v5-ppi into kvmarm-master/next 



* kvm-arm64/vgic-v5-ppi: (40 commits)
  : .
  : Add initial GICv5 support for KVM guests, only adding PPI support
  : for the time being. Patches courtesy of Sascha Bischoff.
  :
  : From the cover letter:
  :
  : "This is v7 of the patch series to add the virtual GICv5 [1] device
  : (vgic_v5). Only PPIs are supported by this initial series, and the
  : vgic_v5 implementation is restricted to the CPU interface,
  : only. Further patch series are to follow in due course, and will add
  : support for SPIs, LPIs, the GICv5 IRS, and the GICv5 ITS."
  : .
  KVM: arm64: selftests: Add no-vgic-v5 selftest
  KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest
  KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI
  Documentation: KVM: Introduce documentation for VGICv5
  KVM: arm64: gic-v5: Probe for GICv5 device
  KVM: arm64: gic-v5: Set ICH_VCTLR_EL2.En on boot
  KVM: arm64: gic-v5: Introduce kvm_arm_vgic_v5_ops and register them
  KVM: arm64: gic-v5: Hide FEAT_GCIE from NV GICv5 guests
  KVM: arm64: gic: Hide GICv5 for protected guests
  KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5
  KVM: arm64: gic-v5: Enlighten arch timer for GICv5
  irqchip/gic-v5: Introduce minimal irq_set_type() for PPIs
  KVM: arm64: gic-v5: Initialise ID and priority bits when resetting vcpu
  KVM: arm64: gic-v5: Create and initialise vgic_v5
  KVM: arm64: gic-v5: Support GICv5 interrupts with KVM_IRQ_LINE
  KVM: arm64: gic-v5: Implement direct injection of PPIs
  KVM: arm64: Introduce set_direct_injection irq_op
  KVM: arm64: gic-v5: Trap and mask guest ICC_PPI_ENABLERx_EL1 writes
  KVM: arm64: gic-v5: Check for pending PPIs
  KVM: arm64: gic-v5: Clear TWI if single task running
  ...

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents 2de32a25 ce29261e

Documentation/virt/kvm/api.rst

+4 −2
Original line number Diff line number Diff line
@@ -907,10 +907,12 @@ The irq_type field has the following values: 
- KVM_ARM_IRQ_TYPE_CPU:

	       out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ

- KVM_ARM_IRQ_TYPE_SPI:

	       in-kernel GIC: SPI, irq_id between 32 and 1019 (incl.)

	       in-kernel GICv2/GICv3: SPI, irq_id between 32 and 1019 (incl.)

               (the vcpu_index field is ignored)

	       in-kernel GICv5: SPI, irq_id between 0 and 65535 (incl.)

- KVM_ARM_IRQ_TYPE_PPI:

	       in-kernel GIC: PPI, irq_id between 16 and 31 (incl.)

	       in-kernel GICv2/GICv3: PPI, irq_id between 16 and 31 (incl.)

	       in-kernel GICv5: PPI, irq_id between 0 and 127 (incl.)



(The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)

Documentation/virt/kvm/devices/arm-vgic-v5.rst

0 → 100644
+50 −0
Original line number Diff line number Diff line 
.. SPDX-License-Identifier: GPL-2.0



====================================================

ARM Virtual Generic Interrupt Controller v5 (VGICv5)

====================================================





Device types supported:

  - KVM_DEV_TYPE_ARM_VGIC_V5     ARM Generic Interrupt Controller v5.0



Only one VGIC instance may be instantiated through this API.  The created VGIC

will act as the VM interrupt controller, requiring emulated user-space devices

to inject interrupts to the VGIC instead of directly to CPUs.



Creating a guest GICv5 device requires a host GICv5 host.  The current VGICv5

device only supports PPI interrupts.  These can either be injected from emulated

in-kernel devices (such as the Arch Timer, or PMU), or via the KVM_IRQ_LINE

ioctl.



Groups:

  KVM_DEV_ARM_VGIC_GRP_CTRL

   Attributes:



    KVM_DEV_ARM_VGIC_CTRL_INIT

      request the initialization of the VGIC, no additional parameter in

      kvm_device_attr.addr. Must be called after all VCPUs have been created.



   KVM_DEV_ARM_VGIC_USERPSPACE_PPIs

      request the mask of userspace-drivable PPIs. Only a subset of the PPIs can

      be directly driven from userspace with GICv5, and the returned mask

      informs userspace of which it is allowed to drive via KVM_IRQ_LINE.



      Userspace must allocate and point to __u64[2] of data in

      kvm_device_attr.addr. When this call returns, the provided memory will be

      populated with the userspace PPI mask. The lower __u64 contains the mask

      for the lower 64 PPIS, with the remaining 64 being in the second __u64.



      This is a read-only attribute, and cannot be set. Attempts to set it are

      rejected.



  Errors:



    =======  ========================================================

    -ENXIO   VGIC not properly configured as required prior to calling

             this attribute

    -ENODEV  no online VCPU

    -ENOMEM  memory shortage when allocating vgic internal data

    -EFAULT  Invalid guest ram access

    -EBUSY   One or more VCPUS are running

    =======  ========================================================

Documentation/virt/kvm/devices/index.rst

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Devices 
   arm-vgic-its

   arm-vgic

   arm-vgic-v3

   arm-vgic-v5

   mpic

   s390_flic

   vcpu

Documentation/virt/kvm/devices/vcpu.rst

+3 −2
Original line number Diff line number Diff line
@@ -37,7 +37,8 @@ Returns: 
A value describing the PMUv3 (Performance Monitor Unit v3) overflow interrupt

number for this vcpu. This interrupt could be a PPI or SPI, but the interrupt

type must be same for each vcpu. As a PPI, the interrupt number is the same for

all vcpus, while as an SPI it must be a separate number per vcpu.

all vcpus, while as an SPI it must be a separate number per vcpu. For

GICv5-based guests, the architected PPI (23) must be used.



1.2 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_INIT

---------------------------------------
@@ -50,7 +51,7 @@ Returns: 
	 -EEXIST  Interrupt number already used

	 -ENODEV  PMUv3 not supported or GIC not initialized

	 -ENXIO   PMUv3 not supported, missing VCPU feature or interrupt

		  number not set

		  number not set (non-GICv5 guests, only)

	 -EBUSY   PMUv3 already initialized

	 =======  ======================================================

arch/arm64/include/asm/el2_setup.h

+2 −0
Original line number Diff line number Diff line
@@ -248,6 +248,8 @@ 
		     ICH_HFGWTR_EL2_ICC_CR0_EL1			| \

		     ICH_HFGWTR_EL2_ICC_APR_EL1)

	msr_s	SYS_ICH_HFGWTR_EL2, x0		// Disable reg write traps

	mov	x0, #(ICH_VCTLR_EL2_En)

	msr_s	SYS_ICH_VCTLR_EL2, x0		// Enable vHPPI selection

.Lskip_gicv5_\@:

.endm