Commit f8c7baf8 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/dsb: Set DSB_SKIP_WAITS_EN chicken bit for LunarLake and onwards 



On LunarLake we are using TRANS_PUSH mechanism to trigger "Frame Change"
event. This way we have more control on when PSR HW is woken up. I.e. not
every display register write is triggering sending update. This allows us
setting DSB_SKIP_WAITS_EN chicken bit as well.

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260127124120.1069026-7-jouni.hogander@intel.com
parent 0dcead77

drivers/gpu/drm/i915/display/intel_dsb.c

+11 −4
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include "intel_display_types.h"

#include "intel_dsb.h"

#include "intel_dsb_regs.h"

#include "intel_psr.h"

#include "intel_vblank.h"

#include "intel_vrr.h"

#include "skl_watermark.h"
@@ -217,18 +218,24 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state, 
 * definitely do not want to skip vblank wait. We also have concern what comes

 * to skipping vblank evasion. I.e. arming registers are latched before we have

 * managed writing them. Due to these reasons we are not setting

 * DSB_SKIP_WAITS_EN.

 * DSB_SKIP_WAITS_EN except when using TRANS_PUSH mechanism to trigger

 * "frame change" event.

 */

static u32 dsb_chicken(struct intel_atomic_state *state,

		       struct intel_crtc *crtc)

{

	const struct intel_crtc_state *new_crtc_state =

		intel_atomic_get_new_crtc_state(state, crtc);

	u32 chicken = intel_psr_use_trans_push(new_crtc_state) ?

		DSB_SKIP_WAITS_EN : 0;



	if (pre_commit_is_vrr_active(state, crtc))

		return DSB_CTRL_WAIT_SAFE_WINDOW |

		chicken |= DSB_CTRL_WAIT_SAFE_WINDOW |

			DSB_CTRL_NO_WAIT_VBLANK |

			DSB_INST_WAIT_SAFE_WINDOW |

			DSB_INST_NO_WAIT_VBLANK;

	else

		return 0;



	return chicken;

}



static bool assert_dsb_has_room(struct intel_dsb *dsb)