Commit f9451374 authored by Chris Brandt's avatar Chris Brandt Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l: Select correct div round macro 



Variable foutvco_rate is an unsigned long, not an unsigned long long.

Cc: stable@kernel.org
Reported-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Closes: https://lore.kernel.org/CAMuHMdVf7dSeqAhtyxDCFuCheQRzwS-8996Rr2Ntui21uiBgdA@mail.gmail.com


Fixes: dabf72b8 ("clk: renesas: rzg2l: Fix FOUTPOSTDIV clk")
Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251114194529.3304361-1-chris.brandt@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent a00655d9

drivers/clk/renesas/rzg2l-cpg.c

+2 −2
Original line number Diff line number Diff line
@@ -572,7 +572,7 @@ rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, 
	foutvco_rate = div_u64(mul_u32_u32(EXTAL_FREQ_IN_MEGA_HZ * MEGA,

					   (params->pl5_intin << 24) + params->pl5_fracin),

			       params->pl5_refdiv) >> 24;

	foutpostdiv_rate = DIV_ROUND_CLOSEST_ULL(foutvco_rate,

	foutpostdiv_rate = DIV_ROUND_CLOSEST(foutvco_rate,

					     params->pl5_postdiv1 * params->pl5_postdiv2);



	return foutpostdiv_rate;