Unverified Commit fa83757d authored by Sheetal's avatar Sheetal Committed by Mark Brown
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ASoC: tegra: ASRC: Update ARAM address



The ARAM address for Tegra264 has been updated. To maintain backward
compatibility given its chip-specific nature, it's now included in the
soc_data.

Signed-off-by: default avatarSheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-6-sheetal@nvidia.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7668c637
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+14 −4
Original line number Diff line number Diff line
// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION. All rights reserved.
//
// tegra186_asrc.c - Tegra186 ASRC driver
//
// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.

#include <linux/clk.h>
#include <linux/delay.h>
@@ -99,7 +98,7 @@ static int tegra186_asrc_runtime_resume(struct device *dev)
	 * sync is done after this to restore other settings.
	 */
	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR,
		     TEGRA186_ASRC_ARAM_START_ADDR);
		     asrc->soc_data->aram_start_addr);
	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB,
		     TEGRA186_ASRC_GLOBAL_EN);

@@ -954,8 +953,17 @@ static const struct regmap_config tegra186_asrc_regmap_config = {
	.cache_type		= REGCACHE_FLAT,
};

static const struct tegra_asrc_soc_data soc_data_tegra186 = {
	.aram_start_addr	= TEGRA186_ASRC_ARAM_START_ADDR,
};

static const struct tegra_asrc_soc_data soc_data_tegra264 = {
	.aram_start_addr	= TEGRA264_ASRC_ARAM_START_ADDR,
};

static const struct of_device_id tegra186_asrc_of_match[] = {
	{ .compatible = "nvidia,tegra186-asrc" },
	{ .compatible = "nvidia,tegra186-asrc", .data = &soc_data_tegra186 },
	{ .compatible = "nvidia,tegra264-asrc", .data = &soc_data_tegra264 },
	{},
};
MODULE_DEVICE_TABLE(of, tegra186_asrc_of_match);
@@ -985,6 +993,8 @@ static int tegra186_asrc_platform_probe(struct platform_device *pdev)
		return PTR_ERR(asrc->regmap);
	}

	asrc->soc_data = of_device_get_match_data(&pdev->dev);

	regcache_cache_only(asrc->regmap, true);

	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CFG,
+8 −4
Original line number Diff line number Diff line
/* SPDX-License-Identifier: GPL-2.0-only */
/*
/* SPDX-License-Identifier: GPL-2.0-only
 * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION. All rights reserved.
 * tegra186_asrc.h - Definitions for Tegra186 ASRC driver
 *
 * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
 *
 */

#ifndef __TEGRA186_ASRC_H__
@@ -94,6 +92,7 @@
#define TEGRA186_ASRC_RATIO_SOURCE_SW				0x1

#define TEGRA186_ASRC_ARAM_START_ADDR				0x3f800000
#define TEGRA264_ASRC_ARAM_START_ADDR				0x8a080000

struct tegra186_asrc_lane {
	unsigned int int_part;
@@ -104,7 +103,12 @@ struct tegra186_asrc_lane {
	unsigned int output_thresh;
};

struct tegra_asrc_soc_data {
	unsigned int aram_start_addr;
};

struct tegra186_asrc {
	const struct tegra_asrc_soc_data *soc_data;
	struct tegra186_asrc_lane lane[TEGRA186_ASRC_STREAM_MAX];
	struct regmap *regmap;
};