Unverified Commit fca0abb2 authored by Juha-Pekka Heikkila's avatar Juha-Pekka Heikkila Committed by Rodrigo Vivi
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drm/i915/display: allow creation of Xe2 ccs framebuffers 



Add I915_FORMAT_MOD_4_TILED_BMG_CCS and I915_FORMAT_MOD_4_TILED_LNL_CCS to possible
created modifier for new framebuffer on Xe driver.

Signed-off-by: default avatarJuha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240816115229.531671-4-juhapekka.heikkila@gmail.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 5151fa35

drivers/gpu/drm/i915/display/intel_display.c

+2 −0
Original line number Diff line number Diff line
@@ -6260,6 +6260,8 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in 
		case I915_FORMAT_MOD_Y_TILED:

		case I915_FORMAT_MOD_Yf_TILED:

		case I915_FORMAT_MOD_4_TILED:

		case I915_FORMAT_MOD_4_TILED_BMG_CCS:

		case I915_FORMAT_MOD_4_TILED_LNL_CCS:

			break;

		default:

			drm_dbg_kms(&i915->drm,

drivers/gpu/drm/i915/display/intel_fb.c

+18 −0
Original line number Diff line number Diff line
@@ -163,6 +163,14 @@ struct intel_modifier_desc { 


static const struct intel_modifier_desc intel_modifiers[] = {

	{

		.modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS,

		.display_ver = { 20, -1 },

		.plane_caps = INTEL_PLANE_CAP_TILING_4,

	}, {

		.modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS,

		.display_ver = { 14, -1 },

		.plane_caps = INTEL_PLANE_CAP_TILING_4,

	}, {

		.modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,

		.display_ver = { 14, 14 },

		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
@@ -437,6 +445,14 @@ static bool plane_has_modifier(struct drm_i915_private *i915, 
	    HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)

		return false;



	if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&

	    (GRAPHICS_VER(i915) < 20 || !IS_DGFX(i915)))

		return false;



	if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS &&

	    (GRAPHICS_VER(i915) < 20 || IS_DGFX(i915)))

		return false;



	return true;

}
@@ -653,6 +669,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) 
			return 128;

		else

			return 512;

	case I915_FORMAT_MOD_4_TILED_BMG_CCS:

	case I915_FORMAT_MOD_4_TILED_LNL_CCS:

	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:

	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:

	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:

drivers/gpu/drm/i915/display/skl_universal_plane.c

+5 −0
Original line number Diff line number Diff line
@@ -537,6 +537,8 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, 
	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:

	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:

	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:

	case I915_FORMAT_MOD_4_TILED_BMG_CCS:

	case I915_FORMAT_MOD_4_TILED_LNL_CCS:

		/*

		 * Align to at least 4x1 main surface

		 * tiles (16K) to match 64B of AUX.
@@ -948,6 +950,9 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) 
		return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;

	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:

		return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;

	case I915_FORMAT_MOD_4_TILED_BMG_CCS:

	case I915_FORMAT_MOD_4_TILED_LNL_CCS:

		return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;

	case I915_FORMAT_MOD_Y_TILED_CCS:

	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:

		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;