Commit fe079ab0 authored by Bharat Bhushan's avatar Bharat Bhushan Committed by David S. Miller
Browse files

cn10k-ipsec: Init hardware for outbound ipsec crypto offload 



One crypto hardware logical function (cpt-lf) per netdev is
required for outbound ipsec crypto offload. Allocate, attach
and initialize one crypto hardware function when enabling
outbound ipsec crypto offload. Crypto hardware function will
be detached and freed on disabling outbound ipsec crypto
offload.

Signed-off-by: default avatarBharat Bhushan <bbhushan2@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a7ef63db

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -13942,6 +13942,7 @@ M: Sunil Goutham <sgoutham@marvell.com> 
M:	Geetha sowjanya <gakula@marvell.com>

M:	Subbaraya Sundeep <sbhatta@marvell.com>

M:	hariprasad <hkelam@marvell.com>

M:	Bharat Bhushan <bbhushan2@marvell.com>

L:	netdev@vger.kernel.org

S:	Supported

F:	drivers/net/ethernet/marvell/octeontx2/nic/

drivers/net/ethernet/marvell/octeontx2/nic/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -15,5 +15,6 @@ rvu_rep-y := rep.o 


rvu_nicpf-$(CONFIG_DCB) += otx2_dcbnl.o

rvu_nicpf-$(CONFIG_MACSEC) += cn10k_macsec.o

rvu_nicpf-$(CONFIG_XFRM_OFFLOAD) += cn10k_ipsec.o



ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

0 → 100644
+415 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Marvell IPSEC offload driver

 *

 * Copyright (C) 2024 Marvell.

 */



#include <net/xfrm.h>

#include <linux/netdevice.h>

#include <linux/bitfield.h>



#include "otx2_common.h"

#include "cn10k_ipsec.h"



static bool is_dev_support_ipsec_offload(struct pci_dev *pdev)

{

	return is_dev_cn10ka_b0(pdev) || is_dev_cn10kb(pdev);

}



static bool cn10k_cpt_device_set_inuse(struct otx2_nic *pf)

{

	enum cn10k_cpt_hw_state_e state;



	while (true) {

		state = atomic_cmpxchg(&pf->ipsec.cpt_state,

				       CN10K_CPT_HW_AVAILABLE,

				       CN10K_CPT_HW_IN_USE);

		if (state == CN10K_CPT_HW_AVAILABLE)

			return true;

		if (state == CN10K_CPT_HW_UNAVAILABLE)

			return false;



		mdelay(1);

	}

}



static void cn10k_cpt_device_set_available(struct otx2_nic *pf)

{

	atomic_set(&pf->ipsec.cpt_state, CN10K_CPT_HW_AVAILABLE);

}



static void  cn10k_cpt_device_set_unavailable(struct otx2_nic *pf)

{

	atomic_set(&pf->ipsec.cpt_state, CN10K_CPT_HW_UNAVAILABLE);

}



static int cn10k_outb_cptlf_attach(struct otx2_nic *pf)

{

	struct rsrc_attach *attach;

	int ret = -ENOMEM;



	mutex_lock(&pf->mbox.lock);

	/* Get memory to put this msg */

	attach = otx2_mbox_alloc_msg_attach_resources(&pf->mbox);

	if (!attach)

		goto unlock;



	attach->cptlfs = true;

	attach->modify = true;



	/* Send attach request to AF */

	ret = otx2_sync_mbox_msg(&pf->mbox);



unlock:

	mutex_unlock(&pf->mbox.lock);

	return ret;

}



static int cn10k_outb_cptlf_detach(struct otx2_nic *pf)

{

	struct rsrc_detach *detach;

	int ret = -ENOMEM;



	mutex_lock(&pf->mbox.lock);

	detach = otx2_mbox_alloc_msg_detach_resources(&pf->mbox);

	if (!detach)

		goto unlock;



	detach->partial = true;

	detach->cptlfs = true;



	/* Send detach request to AF */

	ret = otx2_sync_mbox_msg(&pf->mbox);



unlock:

	mutex_unlock(&pf->mbox.lock);

	return ret;

}



static int cn10k_outb_cptlf_alloc(struct otx2_nic *pf)

{

	struct cpt_lf_alloc_req_msg *req;

	int ret = -ENOMEM;



	mutex_lock(&pf->mbox.lock);

	req = otx2_mbox_alloc_msg_cpt_lf_alloc(&pf->mbox);

	if (!req)

		goto unlock;



	/* PF function */

	req->nix_pf_func = pf->pcifunc;

	/* Enable SE-IE Engine Group */

	req->eng_grpmsk = 1 << CN10K_DEF_CPT_IPSEC_EGRP;



	ret = otx2_sync_mbox_msg(&pf->mbox);



unlock:

	mutex_unlock(&pf->mbox.lock);

	return ret;

}



static void cn10k_outb_cptlf_free(struct otx2_nic *pf)

{

	mutex_lock(&pf->mbox.lock);

	otx2_mbox_alloc_msg_cpt_lf_free(&pf->mbox);

	otx2_sync_mbox_msg(&pf->mbox);

	mutex_unlock(&pf->mbox.lock);

}



static int cn10k_outb_cptlf_config(struct otx2_nic *pf)

{

	struct cpt_inline_ipsec_cfg_msg *req;

	int ret = -ENOMEM;



	mutex_lock(&pf->mbox.lock);

	req = otx2_mbox_alloc_msg_cpt_inline_ipsec_cfg(&pf->mbox);

	if (!req)

		goto unlock;



	req->dir = CPT_INLINE_OUTBOUND;

	req->enable = 1;

	req->nix_pf_func = pf->pcifunc;

	ret = otx2_sync_mbox_msg(&pf->mbox);

unlock:

	mutex_unlock(&pf->mbox.lock);

	return ret;

}



static void cn10k_outb_cptlf_iq_enable(struct otx2_nic *pf)

{

	u64 reg_val;



	/* Set Execution Enable of instruction queue */

	reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);

	reg_val |= BIT_ULL(16);

	otx2_write64(pf, CN10K_CPT_LF_INPROG, reg_val);



	/* Set iqueue's enqueuing */

	reg_val = otx2_read64(pf, CN10K_CPT_LF_CTL);

	reg_val |= BIT_ULL(0);

	otx2_write64(pf, CN10K_CPT_LF_CTL, reg_val);

}



static void cn10k_outb_cptlf_iq_disable(struct otx2_nic *pf)

{

	u32 inflight, grb_cnt, gwb_cnt;

	u32 nq_ptr, dq_ptr;

	int timeout = 20;

	u64 reg_val;

	int cnt;



	/* Disable instructions enqueuing */

	otx2_write64(pf, CN10K_CPT_LF_CTL, 0ull);



	/* Wait for instruction queue to become empty.

	 * CPT_LF_INPROG.INFLIGHT count is zero

	 */

	do {

		reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);

		inflight = FIELD_GET(CPT_LF_INPROG_INFLIGHT, reg_val);

		if (!inflight)

			break;



		usleep_range(10000, 20000);

		if (timeout-- < 0) {

			netdev_err(pf->netdev, "Timeout to cleanup CPT IQ\n");

			break;

		}

	} while (1);



	/* Disable executions in the LF's queue,

	 * the queue should be empty at this point

	 */

	reg_val &= ~BIT_ULL(16);

	otx2_write64(pf, CN10K_CPT_LF_INPROG, reg_val);



	/* Wait for instruction queue to become empty */

	cnt = 0;

	do {

		reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);

		if (reg_val & BIT_ULL(31))

			cnt = 0;

		else

			cnt++;

		reg_val = otx2_read64(pf, CN10K_CPT_LF_Q_GRP_PTR);

		nq_ptr = FIELD_GET(CPT_LF_Q_GRP_PTR_DQ_PTR, reg_val);

		dq_ptr = FIELD_GET(CPT_LF_Q_GRP_PTR_DQ_PTR, reg_val);

	} while ((cnt < 10) && (nq_ptr != dq_ptr));



	cnt = 0;

	do {

		reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);

		inflight = FIELD_GET(CPT_LF_INPROG_INFLIGHT, reg_val);

		grb_cnt = FIELD_GET(CPT_LF_INPROG_GRB_CNT, reg_val);

		gwb_cnt = FIELD_GET(CPT_LF_INPROG_GWB_CNT, reg_val);

		if (inflight == 0 && gwb_cnt < 40 &&

		    (grb_cnt == 0 || grb_cnt == 40))

			cnt++;

		else

			cnt = 0;

	} while (cnt < 10);

}



/* Allocate memory for CPT outbound Instruction queue.

 * Instruction queue memory format is:

 *      -----------------------------

 *     | Instruction Group memory    |

 *     |  (CPT_LF_Q_SIZE[SIZE_DIV40] |

 *     |   x 16 Bytes)               |

 *     |                             |

 *      ----------------------------- <-- CPT_LF_Q_BASE[ADDR]

 *     | Flow Control (128 Bytes)    |

 *     |                             |

 *      -----------------------------

 *     |  Instruction Memory         |

 *     |  (CPT_LF_Q_SIZE[SIZE_DIV40] |

 *     |   × 40 × 64 bytes)          |

 *     |                             |

 *      -----------------------------

 */

static int cn10k_outb_cptlf_iq_alloc(struct otx2_nic *pf)

{

	struct cn10k_cpt_inst_queue *iq = &pf->ipsec.iq;



	iq->size = CN10K_CPT_INST_QLEN_BYTES + CN10K_CPT_Q_FC_LEN +

		    CN10K_CPT_INST_GRP_QLEN_BYTES + OTX2_ALIGN;



	iq->real_vaddr = dma_alloc_coherent(pf->dev, iq->size,

					    &iq->real_dma_addr, GFP_KERNEL);

	if (!iq->real_vaddr)

		return -ENOMEM;



	/* iq->vaddr/dma_addr points to Flow Control location */

	iq->vaddr = iq->real_vaddr + CN10K_CPT_INST_GRP_QLEN_BYTES;

	iq->dma_addr = iq->real_dma_addr + CN10K_CPT_INST_GRP_QLEN_BYTES;



	/* Align pointers */

	iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_ALIGN);

	iq->dma_addr = PTR_ALIGN(iq->dma_addr, OTX2_ALIGN);

	return 0;

}



static void cn10k_outb_cptlf_iq_free(struct otx2_nic *pf)

{

	struct cn10k_cpt_inst_queue *iq = &pf->ipsec.iq;



	if (iq->real_vaddr)

		dma_free_coherent(pf->dev, iq->size, iq->real_vaddr,

				  iq->real_dma_addr);



	iq->real_vaddr = NULL;

	iq->vaddr = NULL;

}



static int cn10k_outb_cptlf_iq_init(struct otx2_nic *pf)

{

	u64 reg_val;

	int ret;



	/* Allocate Memory for CPT IQ */

	ret = cn10k_outb_cptlf_iq_alloc(pf);

	if (ret)

		return ret;



	/* Disable IQ */

	cn10k_outb_cptlf_iq_disable(pf);



	/* Set IQ base address */

	otx2_write64(pf, CN10K_CPT_LF_Q_BASE, pf->ipsec.iq.dma_addr);



	/* Set IQ size */

	reg_val = FIELD_PREP(CPT_LF_Q_SIZE_DIV40, CN10K_CPT_SIZE_DIV40 +

			     CN10K_CPT_EXTRA_SIZE_DIV40);

	otx2_write64(pf, CN10K_CPT_LF_Q_SIZE, reg_val);



	return 0;

}



static int cn10k_outb_cptlf_init(struct otx2_nic *pf)

{

	int ret;



	/* Initialize CPTLF Instruction Queue (IQ) */

	ret = cn10k_outb_cptlf_iq_init(pf);

	if (ret)

		return ret;



	/* Configure CPTLF for outbound ipsec offload */

	ret = cn10k_outb_cptlf_config(pf);

	if (ret)

		goto iq_clean;



	/* Enable CPTLF IQ */

	cn10k_outb_cptlf_iq_enable(pf);

	return 0;

iq_clean:

	cn10k_outb_cptlf_iq_free(pf);

	return ret;

}



static int cn10k_outb_cpt_init(struct net_device *netdev)

{

	struct otx2_nic *pf = netdev_priv(netdev);

	int ret;



	/* Attach a CPT LF for outbound ipsec offload */

	ret = cn10k_outb_cptlf_attach(pf);

	if (ret)

		return ret;



	/* Allocate a CPT LF for outbound ipsec offload */

	ret = cn10k_outb_cptlf_alloc(pf);

	if (ret)

		goto detach;



	/* Initialize the CPTLF for outbound ipsec offload */

	ret = cn10k_outb_cptlf_init(pf);

	if (ret)

		goto lf_free;



	pf->ipsec.io_addr = (__force u64)otx2_get_regaddr(pf,

						CN10K_CPT_LF_NQX(0));



	/* Set ipsec offload enabled for this device */

	pf->flags |= OTX2_FLAG_IPSEC_OFFLOAD_ENABLED;



	cn10k_cpt_device_set_available(pf);

	return 0;



lf_free:

	cn10k_outb_cptlf_free(pf);

detach:

	cn10k_outb_cptlf_detach(pf);

	return ret;

}



static int cn10k_outb_cpt_clean(struct otx2_nic *pf)

{

	int ret;



	if (!cn10k_cpt_device_set_inuse(pf)) {

		netdev_err(pf->netdev, "CPT LF device unavailable\n");

		return -ENODEV;

	}



	/* Set ipsec offload disabled for this device */

	pf->flags &= ~OTX2_FLAG_IPSEC_OFFLOAD_ENABLED;



	/* Disable CPTLF Instruction Queue (IQ) */

	cn10k_outb_cptlf_iq_disable(pf);



	/* Set IQ base address and size to 0 */

	otx2_write64(pf, CN10K_CPT_LF_Q_BASE, 0);

	otx2_write64(pf, CN10K_CPT_LF_Q_SIZE, 0);



	/* Free CPTLF IQ */

	cn10k_outb_cptlf_iq_free(pf);



	/* Free and detach CPT LF */

	cn10k_outb_cptlf_free(pf);

	ret = cn10k_outb_cptlf_detach(pf);

	if (ret)

		netdev_err(pf->netdev, "Failed to detach CPT LF\n");



	cn10k_cpt_device_set_unavailable(pf);

	return ret;

}



int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable)

{

	struct otx2_nic *pf = netdev_priv(netdev);



	/* IPsec offload supported on cn10k */

	if (!is_dev_support_ipsec_offload(pf->pdev))

		return -EOPNOTSUPP;



	/* Initialize CPT for outbound ipsec offload */

	if (enable)

		return cn10k_outb_cpt_init(netdev);



	return cn10k_outb_cpt_clean(pf);

}



int cn10k_ipsec_init(struct net_device *netdev)

{

	struct otx2_nic *pf = netdev_priv(netdev);



	if (!is_dev_support_ipsec_offload(pf->pdev))

		return 0;



	cn10k_cpt_device_set_unavailable(pf);

	return 0;

}

EXPORT_SYMBOL(cn10k_ipsec_init);



void cn10k_ipsec_clean(struct otx2_nic *pf)

{

	if (!is_dev_support_ipsec_offload(pf->pdev))

		return;



	if (!(pf->flags & OTX2_FLAG_IPSEC_OFFLOAD_ENABLED))

		return;



	cn10k_outb_cpt_clean(pf);

}

EXPORT_SYMBOL(cn10k_ipsec_clean);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

0 → 100644
+109 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Marvell IPSEC offload driver

 *

 * Copyright (C) 2024 Marvell.

 */



#ifndef CN10K_IPSEC_H

#define CN10K_IPSEC_H



#include <linux/types.h>



/* CPT instruction size in bytes */

#define CN10K_CPT_INST_SIZE	64



/* CPT instruction (CPT_INST_S) queue length */

#define CN10K_CPT_INST_QLEN	8200



/* CPT instruction queue size passed to HW is in units of

 * 40*CPT_INST_S messages.

 */

#define CN10K_CPT_SIZE_DIV40 (CN10K_CPT_INST_QLEN / 40)



/* CPT needs 320 free entries */

#define CN10K_CPT_INST_QLEN_EXTRA_BYTES	(320 * CN10K_CPT_INST_SIZE)

#define CN10K_CPT_EXTRA_SIZE_DIV40	(320 / 40)



/* CPT instruction queue length in bytes */

#define CN10K_CPT_INST_QLEN_BYTES					\

		((CN10K_CPT_SIZE_DIV40 * 40 * CN10K_CPT_INST_SIZE) +	\

		CN10K_CPT_INST_QLEN_EXTRA_BYTES)



/* CPT instruction group queue length in bytes */

#define CN10K_CPT_INST_GRP_QLEN_BYTES					\

		((CN10K_CPT_SIZE_DIV40 + CN10K_CPT_EXTRA_SIZE_DIV40) * 16)



/* CPT FC length in bytes */

#define CN10K_CPT_Q_FC_LEN 128



/* Default CPT engine group for ipsec offload */

#define CN10K_DEF_CPT_IPSEC_EGRP 1



/* CN10K CPT LF registers */

#define CPT_LFBASE			(BLKTYPE_CPT << RVU_FUNC_BLKADDR_SHIFT)

#define CN10K_CPT_LF_CTL		(CPT_LFBASE | 0x10)

#define CN10K_CPT_LF_INPROG		(CPT_LFBASE | 0x40)

#define CN10K_CPT_LF_Q_BASE		(CPT_LFBASE | 0xf0)

#define CN10K_CPT_LF_Q_SIZE		(CPT_LFBASE | 0x100)

#define CN10K_CPT_LF_Q_INST_PTR		(CPT_LFBASE | 0x110)

#define CN10K_CPT_LF_Q_GRP_PTR		(CPT_LFBASE | 0x120)

#define CN10K_CPT_LF_NQX(a)		(CPT_LFBASE | 0x400 | (a) << 3)

#define CN10K_CPT_LF_CTX_FLUSH		(CPT_LFBASE | 0x510)



struct cn10k_cpt_inst_queue {

	u8 *vaddr;

	u8 *real_vaddr;

	dma_addr_t dma_addr;

	dma_addr_t real_dma_addr;

	u32 size;

};



enum cn10k_cpt_hw_state_e {

	CN10K_CPT_HW_UNAVAILABLE,

	CN10K_CPT_HW_AVAILABLE,

	CN10K_CPT_HW_IN_USE

};



struct cn10k_ipsec {

	/* Outbound CPT */

	u64 io_addr;

	atomic_t cpt_state;

	struct cn10k_cpt_inst_queue iq;

};



/* CPT LF_INPROG Register */

#define CPT_LF_INPROG_INFLIGHT	GENMASK_ULL(8, 0)

#define CPT_LF_INPROG_GRB_CNT	GENMASK_ULL(39, 32)

#define CPT_LF_INPROG_GWB_CNT	GENMASK_ULL(47, 40)



/* CPT LF_Q_GRP_PTR Register */

#define CPT_LF_Q_GRP_PTR_DQ_PTR	GENMASK_ULL(14, 0)

#define CPT_LF_Q_GRP_PTR_NQ_PTR	GENMASK_ULL(46, 32)



/* CPT LF_Q_SIZE Register */

#define CPT_LF_Q_BASE_ADDR GENMASK_ULL(52, 7)



/* CPT LF_Q_SIZE Register */

#define CPT_LF_Q_SIZE_DIV40 GENMASK_ULL(14, 0)



#ifdef CONFIG_XFRM_OFFLOAD

int cn10k_ipsec_init(struct net_device *netdev);

void cn10k_ipsec_clean(struct otx2_nic *pf);

int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable);

#else

static inline __maybe_unused int cn10k_ipsec_init(struct net_device *netdev)

{

	return 0;

}



static inline __maybe_unused void cn10k_ipsec_clean(struct otx2_nic *pf)

{

}



static inline __maybe_unused

int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable)

{

	return 0;

}

#endif

#endif // CN10K_IPSEC_H

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

+18 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include <rvu_trace.h>

#include "qos.h"

#include "rep.h"

#include "cn10k_ipsec.h"



/* IPv4 flag more fragment bit */

#define IPV4_FLAG_MORE				0x20
@@ -40,6 +41,7 @@ 
#define PCI_DEVID_OCTEONTX2_RVU_AFVF		0xA0F8



#define PCI_SUBSYS_DEVID_96XX_RVU_PFVF		0xB200

#define PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF	0xB900

#define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF	0xBD00



#define PCI_DEVID_OCTEONTX2_SDP_REP		0xA0F7
@@ -448,6 +450,7 @@ struct otx2_nic { 
#define OTX2_FLAG_TC_MARK_ENABLED		BIT_ULL(17)

#define OTX2_FLAG_REP_MODE_ENABLED		 BIT_ULL(18)

#define OTX2_FLAG_PORT_UP			BIT_ULL(19)

#define OTX2_FLAG_IPSEC_OFFLOAD_ENABLED		BIT_ULL(20)

	u64			flags;

	u64			*cq_op_addr;
@@ -522,6 +525,9 @@ struct otx2_nic { 
	u16			rep_pf_map[RVU_MAX_REP];

	u16			esw_mode;

#endif



	/* Inline ipsec */

	struct cn10k_ipsec	ipsec;

};



static inline bool is_otx2_lbkvf(struct pci_dev *pdev)
@@ -572,6 +578,15 @@ static inline bool is_dev_cn10kb(struct pci_dev *pdev) 
	return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF;

}



static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev)

{

	if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF &&

	    (pdev->revision & 0xFF) == 0x54)

		return true;



	return false;

}



static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)

{

	struct otx2_hw *hw = &pfvf->hw;
@@ -621,6 +636,9 @@ static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 
	case BLKTYPE_NPA:

		blkaddr = BLKADDR_NPA;

		break;

	case BLKTYPE_CPT:

		blkaddr = BLKADDR_CPT0;

		break;

	default:

		blkaddr = BLKADDR_RVUM;

		break;