Commit ff69bba0 authored by Boyuan Zhang's avatar Boyuan Zhang Committed by Alex Deucher
Browse files

drm/amd/pm: add inst to dpm_set_powergating_by_smu 



Add an instance parameter to amdgpu_dpm_set_powergating_by_smu() function,
and use the instance to call set_powergating_by_smu().

v2: remove duplicated functions.

remove for-loop in amdgpu_dpm_set_powergating_by_smu(), and temporarily
move it to amdgpu_dpm_enable_vcn(), in order to keep the exact same logic
as before, until further separation in next patch.

v3: drop SI logic in amdgpu_dpm_enable_vcn().

Signed-off-by: default avatarBoyuan Zhang <boyuan.zhang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 697cb5cc

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c

+7 −7
Original line number Diff line number Diff line
@@ -140,7 +140,7 @@ static int acp_poweroff(struct generic_pm_domain *genpd) 
	 * 2. power off the acp tiles

	 * 3. check and enter ulv state

	 */

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);

	return 0;

}
@@ -157,7 +157,7 @@ static int acp_poweron(struct generic_pm_domain *genpd) 
	 * 2. turn on acp clock

	 * 3. power on acp tiles

	 */

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);

	return 0;

}
@@ -236,7 +236,7 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block) 
			    ip_block->version->major, ip_block->version->minor);

	/* -ENODEV means board uses AZ rather than ACP */

	if (r == -ENODEV) {

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);

		return 0;

	} else if (r) {

		return r;
@@ -508,7 +508,7 @@ static int acp_hw_fini(struct amdgpu_ip_block *ip_block) 


	/* return early if no ACP */

	if (!adev->acp.acp_genpd) {

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);

		return 0;

	}
@@ -565,7 +565,7 @@ static int acp_suspend(struct amdgpu_ip_block *ip_block) 


	/* power up on suspend */

	if (!adev->acp.acp_cell)

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);

	return 0;

}
@@ -575,7 +575,7 @@ static int acp_resume(struct amdgpu_ip_block *ip_block) 


	/* power down again on resume */

	if (!adev->acp.acp_cell)

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);

	return 0;

}
@@ -596,7 +596,7 @@ static int acp_set_powergating_state(void *handle, 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	bool enable = (state == AMD_PG_STATE_GATE);



	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -3478,7 +3478,7 @@ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) 
	WARN_ON_ONCE(adev->gfx.gfx_off_state);

	WARN_ON_ONCE(adev->gfx.gfx_off_req_count);



	if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))

	if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true, 0))

		adev->gfx.gfx_off_state = true;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+2 −2
Original line number Diff line number Diff line
@@ -806,7 +806,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) 
			/* If going to s2idle, no need to wait */

			if (adev->in_s0ix) {

				if (!amdgpu_dpm_set_powergating_by_smu(adev,

						AMD_IP_BLOCK_TYPE_GFX, true))

						AMD_IP_BLOCK_TYPE_GFX, true, 0))

					adev->gfx.gfx_off_state = true;

			} else {

				schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
@@ -818,7 +818,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) 
			cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);



			if (adev->gfx.gfx_off_state &&

			    !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {

			    !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false, 0)) {

				adev->gfx.gfx_off_state = false;



				if (adev->gfx.funcs->init_spm_golden) {

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+1 −1
Original line number Diff line number Diff line
@@ -5319,7 +5319,7 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade 
	    (adev->asic_type == CHIP_POLARIS12) ||

	    (adev->asic_type == CHIP_VEGAM))

		/* Send msg to SMU via Powerplay */

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable, 0);



	WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);

}

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+1 −1
Original line number Diff line number Diff line
@@ -356,7 +356,7 @@ static void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, 
	if (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)

		amdgpu_dpm_set_powergating_by_smu(adev,

						  AMD_IP_BLOCK_TYPE_GMC,

						  enable);

						  enable, 0);

}



static int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)