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Merge branch 'net-enetc-safely-reinitialize-tx-bd-ring-when-it-has-unsent-frames'

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Wei Fang says:

====================
net: enetc: safely reinitialize TX BD ring when it has unsent frames

Currently the driver does not reset the producer index register (PIR) and
consumer index register (CIR) when initializing a TX BD ring. The driver
only reads the PIR and CIR and initializes the software indexes. If the
TX BD ring is reinitialized when it still contains unsent frames, its PIR
and CIR will not be equal after the reinitialization. However, the BDs
between CIR and PIR have been freed and become invalid and this can lead
to a hardware malfunction, causing the TX BD ring will not work properly.

Since the PIR and CIR are sofeware-configurable on ENETC v4. Therefore,
the driver must reset them if they are not equal when reinitializing
the TX BD ring.

However, resetting the PIR and CIR alone is insufficient, it cannot
completely solve the problem. When a link-down event occurs while the TX
BD ring is transmitting frames, subsequent reinitialization of the TX BD
ring may cause it to malfunction. Because enetc4_pl_mac_link_down() only
clears PMa_COMMAND_CONFIG[TX_EN] to disable MAC transmit data path. It
doesn't set PORT[TXDIS] to 1 to flush the TX BD ring. Therefore, it is
not safe to reinitialize the TX BD ring at this point.

To safely reinitialize the TX BD ring after a link-down event, we checked
with the NETC IP team, a proper Ethernet MAC graceful stop is necessary.
Therefore, add the Ethernet MAC graceful stop to the link-down event
handler enetc4_pl_mac_link_down(). Note that this patch set is not
applicable to ENETC v1 (LS1028A).
====================

Link: https://patch.msgid.link/20260324062121.2745033-1-wei.fang@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
2026-03-26 20:19:08 -07:00
parent e8e44c98f7 f2df9567b1
commit 04f272188f
3 changed files with 127 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/net/ethernet/freescale/enetc/enetc.c
View File

@@ -2578,6 +2578,7 @@ EXPORT_SYMBOL_GPL(enetc_free_si_resources);
static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
{
struct enetc_si *si = container_of(hw, struct enetc_si, hw);
int idx = tx_ring->index;
u32 tbmr;
@@ -2591,10 +2592,20 @@ static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
ENETC_RTBLENR_LEN(tx_ring->bd_count));
/* clearing PI/CI registers for Tx not supported, adjust sw indexes */
/* For ENETC v1, clearing PI/CI registers for Tx not supported,
* adjust sw indexes
*/
tx_ring->next_to_use = enetc_txbdr_rd(hw, idx, ENETC_TBPIR);
tx_ring->next_to_clean = enetc_txbdr_rd(hw, idx, ENETC_TBCIR);
if (tx_ring->next_to_use != tx_ring->next_to_clean &&
!is_enetc_rev1(si)) {
tx_ring->next_to_use = 0;
tx_ring->next_to_clean = 0;
enetc_txbdr_wr(hw, idx, ENETC_TBPIR, 0);
enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0);
}
/* enable Tx ints by setting pkt thr to 1 */
enetc_txbdr_wr(hw, idx, ENETC_TBICR0, ENETC_TBICR0_ICEN | 0x1);

11
drivers/net/ethernet/freescale/enetc/enetc4_hw.h
View File

@@ -134,6 +134,12 @@
/* Port operational register */
#define ENETC4_POR 0x4100
#define POR_TXDIS BIT(0)
#define POR_RXDIS BIT(1)
/* Port status register */
#define ENETC4_PSR 0x4104
#define PSR_RX_BUSY BIT(1)
/* Port traffic class a transmit maximum SDU register */
#define ENETC4_PTCTMSDUR(a) ((a) * 0x20 + 0x4208)
@@ -173,6 +179,11 @@
/* Port internal MDIO base address, use to access PCS */
#define ENETC4_PM_IMDIO_BASE 0x5030
/* Port MAC 0/1 Interrupt Event Register */
#define ENETC4_PM_IEVENT(mac) (0x5040 + (mac) * 0x400)
#define PM_IEVENT_TX_EMPTY BIT(5)
#define PM_IEVENT_RX_EMPTY BIT(6)
/* Port MAC 0/1 Pause Quanta Register */
#define ENETC4_PM_PAUSE_QUANTA(mac) (0x5054 + (mac) * 0x400)

118
drivers/net/ethernet/freescale/enetc/enetc4_pf.c
View File

@@ -444,20 +444,11 @@ static void enetc4_set_trx_frame_size(struct enetc_pf *pf)
enetc4_pf_reset_tc_msdu(&si->hw);
}
static void enetc4_enable_trx(struct enetc_pf *pf)
{
struct enetc_hw *hw = &pf->si->hw;
/* Enable port transmit/receive */
enetc_port_wr(hw, ENETC4_POR, 0);
}
static void enetc4_configure_port(struct enetc_pf *pf)
{
enetc4_configure_port_si(pf);
enetc4_set_trx_frame_size(pf);
enetc_set_default_rss_key(pf);
enetc4_enable_trx(pf);
}
static int enetc4_init_ntmp_user(struct enetc_si *si)
@@ -801,15 +792,112 @@ static void enetc4_set_tx_pause(struct enetc_pf *pf, int num_rxbdr, bool tx_paus
enetc_port_wr(hw, ENETC4_PPAUOFFTR, pause_off_thresh);
}
static void enetc4_enable_mac(struct enetc_pf *pf, bool en)
static void enetc4_mac_wait_tx_empty(struct enetc_si *si, int mac)
{
u32 val;
if (read_poll_timeout(enetc_port_rd, val,
val & PM_IEVENT_TX_EMPTY,
100, 10000, false, &si->hw,
ENETC4_PM_IEVENT(mac)))
dev_warn(&si->pdev->dev,
"MAC %d TX is not empty\n", mac);
}
static void enetc4_mac_tx_graceful_stop(struct enetc_pf *pf)
{
struct enetc_hw *hw = &pf->si->hw;
struct enetc_si *si = pf->si;
u32 val;
val = enetc_port_rd(hw, ENETC4_POR);
val |= POR_TXDIS;
enetc_port_wr(hw, ENETC4_POR, val);
if (enetc_is_pseudo_mac(si))
return;
enetc4_mac_wait_tx_empty(si, 0);
if (si->hw_features & ENETC_SI_F_QBU)
enetc4_mac_wait_tx_empty(si, 1);
val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0));
val &= ~PM_CMD_CFG_TX_EN;
enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val);
}
static void enetc4_mac_tx_enable(struct enetc_pf *pf)
{
struct enetc_hw *hw = &pf->si->hw;
struct enetc_si *si = pf->si;
u32 val;
val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0));
val &= ~(PM_CMD_CFG_TX_EN | PM_CMD_CFG_RX_EN);
val |= en ? (PM_CMD_CFG_TX_EN | PM_CMD_CFG_RX_EN) : 0;
val |= PM_CMD_CFG_TX_EN;
enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val);
val = enetc_port_rd(hw, ENETC4_POR);
val &= ~POR_TXDIS;
enetc_port_wr(hw, ENETC4_POR, val);
}
static void enetc4_mac_wait_rx_empty(struct enetc_si *si, int mac)
{
u32 val;
if (read_poll_timeout(enetc_port_rd, val,
val & PM_IEVENT_RX_EMPTY,
100, 10000, false, &si->hw,
ENETC4_PM_IEVENT(mac)))
dev_warn(&si->pdev->dev,
"MAC %d RX is not empty\n", mac);
}
static void enetc4_mac_rx_graceful_stop(struct enetc_pf *pf)
{
struct enetc_hw *hw = &pf->si->hw;
struct enetc_si *si = pf->si;
u32 val;
if (enetc_is_pseudo_mac(si))
goto check_rx_busy;
if (si->hw_features & ENETC_SI_F_QBU) {
val = enetc_port_rd(hw, ENETC4_PM_CMD_CFG(1));
val &= ~PM_CMD_CFG_RX_EN;
enetc_port_wr(hw, ENETC4_PM_CMD_CFG(1), val);
enetc4_mac_wait_rx_empty(si, 1);
}
val = enetc_port_rd(hw, ENETC4_PM_CMD_CFG(0));
val &= ~PM_CMD_CFG_RX_EN;
enetc_port_wr(hw, ENETC4_PM_CMD_CFG(0), val);
enetc4_mac_wait_rx_empty(si, 0);
check_rx_busy:
if (read_poll_timeout(enetc_port_rd, val,
!(val & PSR_RX_BUSY),
100, 10000, false, hw,
ENETC4_PSR))
dev_warn(&si->pdev->dev, "Port RX busy\n");
val = enetc_port_rd(hw, ENETC4_POR);
val |= POR_RXDIS;
enetc_port_wr(hw, ENETC4_POR, val);
}
static void enetc4_mac_rx_enable(struct enetc_pf *pf)
{
struct enetc_hw *hw = &pf->si->hw;
struct enetc_si *si = pf->si;
u32 val;
val = enetc_port_rd(hw, ENETC4_POR);
val &= ~POR_RXDIS;
enetc_port_wr(hw, ENETC4_POR, val);
val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0));
val |= PM_CMD_CFG_RX_EN;
enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val);
}
@@ -853,7 +941,8 @@ static void enetc4_pl_mac_link_up(struct phylink_config *config,
enetc4_set_hd_flow_control(pf, hd_fc);
enetc4_set_tx_pause(pf, priv->num_rx_rings, tx_pause);
enetc4_set_rx_pause(pf, rx_pause);
enetc4_enable_mac(pf, true);
enetc4_mac_tx_enable(pf);
enetc4_mac_rx_enable(pf);
}
static void enetc4_pl_mac_link_down(struct phylink_config *config,
@@ -862,7 +951,8 @@ static void enetc4_pl_mac_link_down(struct phylink_config *config,
{
struct enetc_pf *pf = phylink_to_enetc_pf(config);
enetc4_enable_mac(pf, false);
enetc4_mac_rx_graceful_stop(pf);
enetc4_mac_tx_graceful_stop(pf);
}
static const struct phylink_mac_ops enetc_pl_mac_ops = {