Commit 0bd9b121 authored by Yassine Oudjana's avatar Yassine Oudjana Committed by Stephen Boyd
Browse files

clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers 



Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets
on MT6735.

Signed-off-by: default avatarYassine Oudjana <y.oudjana@protonmail.com>
Link: https://lore.kernel.org/r/20241106111402.200940-3-y.oudjana@protonmail.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent a7479860

MAINTAINERS

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@@ -14534,9 +14534,13 @@ L: linux-clk@vger.kernel.org 
L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	drivers/clk/mediatek/clk-mt6735-apmixedsys.c

F:	drivers/clk/mediatek/clk-mt6735-imgsys.c

F:	drivers/clk/mediatek/clk-mt6735-infracfg.c

F:	drivers/clk/mediatek/clk-mt6735-mfgcfg.c

F:	drivers/clk/mediatek/clk-mt6735-pericfg.c

F:	drivers/clk/mediatek/clk-mt6735-topckgen.c

F:	drivers/clk/mediatek/clk-mt6735-vdecsys.c

F:	drivers/clk/mediatek/clk-mt6735-vencsys.c

F:	include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h

F:	include/dt-bindings/clock/mediatek,mt6735-imgsys.h

F:	include/dt-bindings/clock/mediatek,mt6735-infracfg.h

drivers/clk/mediatek/Kconfig

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@@ -133,6 +133,34 @@ config COMMON_CLK_MT6735 
	  by apmixedsys, topckgen, infracfg and pericfg on the

	  MediaTek MT6735 SoC.



config COMMON_CLK_MT6735_IMGSYS

	tristate "Clock driver for MediaTek MT6735 imgsys"

	depends on COMMON_CLK_MT6735

	help

	  This enables a driver for clocks provided by imgsys

	  on the MediaTek MT6735 SoC.



config COMMON_CLK_MT6735_MFGCFG

	tristate "Clock driver for MediaTek MT6735 mfgcfg"

	depends on COMMON_CLK_MT6735

	help

	  This enables a driver for clocks and resets provided

	  by mfgcfg on the MediaTek MT6735 SoC.



config COMMON_CLK_MT6735_VDECSYS

	tristate "Clock driver for MediaTek MT6735 vdecsys"

	depends on COMMON_CLK_MT6735

	help

	  This enables a driver for clocks and resets provided

	  by vdecsys on the MediaTek MT6735 SoC.



config COMMON_CLK_MT6735_VENCSYS

	tristate "Clock driver for MediaTek MT6735 vencsys"

	depends on COMMON_CLK_MT6735

	help

	  This enables a driver for clocks provided by vencsys

	  on the MediaTek MT6735 SoC.



config COMMON_CLK_MT6765

       bool "Clock driver for MediaTek MT6765"

       depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

drivers/clk/mediatek/Makefile

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@@ -3,6 +3,10 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed. 
obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o



obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o

obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o

obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o

obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o

obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o

obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o

obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o

obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o

drivers/clk/mediatek/clk-mt6735-imgsys.c

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>

 */



#include <linux/clk-provider.h>

#include <linux/platform_device.h>



#include "clk-gate.h"

#include "clk-mtk.h"



#include <dt-bindings/clock/mediatek,mt6735-imgsys.h>



#define IMG_CG_CON			0x00

#define IMG_CG_SET			0x04

#define IMG_CG_CLR			0x08



static struct mtk_gate_regs imgsys_cg_regs = {

	.set_ofs = IMG_CG_SET,

	.clr_ofs = IMG_CG_CLR,

	.sta_ofs = IMG_CG_CON,

};



static const struct mtk_gate imgsys_gates[] = {

	GATE_MTK(CLK_IMG_SMI_LARB2, "smi_larb2", "mm_sel", &imgsys_cg_regs, 0, &mtk_clk_gate_ops_setclr),

	GATE_MTK(CLK_IMG_CAM_SMI, "cam_smi", "mm_sel", &imgsys_cg_regs, 5, &mtk_clk_gate_ops_setclr),

	GATE_MTK(CLK_IMG_CAM_CAM, "cam_cam", "mm_sel", &imgsys_cg_regs, 6, &mtk_clk_gate_ops_setclr),

	GATE_MTK(CLK_IMG_SEN_TG, "sen_tg", "mm_sel", &imgsys_cg_regs, 7, &mtk_clk_gate_ops_setclr),

	GATE_MTK(CLK_IMG_SEN_CAM, "sen_cam", "mm_sel", &imgsys_cg_regs, 8, &mtk_clk_gate_ops_setclr),

	GATE_MTK(CLK_IMG_CAM_SV, "cam_sv", "mm_sel", &imgsys_cg_regs, 9, &mtk_clk_gate_ops_setclr),

	GATE_MTK(CLK_IMG_SUFOD, "sufod", "mm_sel", &imgsys_cg_regs, 10, &mtk_clk_gate_ops_setclr),

	GATE_MTK(CLK_IMG_FD, "fd", "mm_sel", &imgsys_cg_regs, 11, &mtk_clk_gate_ops_setclr),

};



static const struct mtk_clk_desc imgsys_clks = {

	.clks = imgsys_gates,

	.num_clks = ARRAY_SIZE(imgsys_gates),

};



static const struct of_device_id of_match_mt6735_imgsys[] = {

	{ .compatible = "mediatek,mt6735-imgsys", .data = &imgsys_clks },

	{ /* sentinel */ }

};



static struct platform_driver clk_mt6735_imgsys = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt6735-imgsys",

		.of_match_table = of_match_mt6735_imgsys,

	},

};

module_platform_driver(clk_mt6735_imgsys);



MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");

MODULE_DESCRIPTION("MediaTek MT6735 imgsys clock driver");

MODULE_LICENSE("GPL");

drivers/clk/mediatek/clk-mt6735-mfgcfg.c

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>

 */



#include <linux/clk-provider.h>

#include <linux/platform_device.h>



#include "clk-gate.h"

#include "clk-mtk.h"



#include <dt-bindings/clock/mediatek,mt6735-mfgcfg.h>



#define MFG_CG_CON			0x00

#define MFG_CG_SET			0x04

#define MFG_CG_CLR			0x08

#define MFG_RESET			0x0c



static struct mtk_gate_regs mfgcfg_cg_regs = {

	.set_ofs = MFG_CG_SET,

	.clr_ofs = MFG_CG_CLR,

	.sta_ofs = MFG_CG_CON,

};



static const struct mtk_gate mfgcfg_gates[] = {

	GATE_MTK(CLK_MFG_BG3D, "bg3d", "mfg_sel", &mfgcfg_cg_regs, 0, &mtk_clk_gate_ops_setclr),

};



static u16 mfgcfg_rst_ofs[] = { MFG_RESET };



static const struct mtk_clk_rst_desc mfgcfg_resets = {

	.version = MTK_RST_SIMPLE,

	.rst_bank_ofs = mfgcfg_rst_ofs,

	.rst_bank_nr = ARRAY_SIZE(mfgcfg_rst_ofs)

};



static const struct mtk_clk_desc mfgcfg_clks = {

	.clks = mfgcfg_gates,

	.num_clks = ARRAY_SIZE(mfgcfg_gates),



	.rst_desc = &mfgcfg_resets

};



static const struct of_device_id of_match_mt6735_mfgcfg[] = {

	{ .compatible = "mediatek,mt6735-mfgcfg", .data = &mfgcfg_clks },

	{ /* sentinel */ }

};



static struct platform_driver clk_mt6735_mfgcfg = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt6735-mfgcfg",

		.of_match_table = of_match_mt6735_mfgcfg,

	},

};

module_platform_driver(clk_mt6735_mfgcfg);



MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");

MODULE_DESCRIPTION("Mediatek MT6735 mfgcfg clock and reset driver");

MODULE_LICENSE("GPL");