Commit 0c520ad4 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr/gf117-: make ppc_nr[gpc] accurate 



We're going to be pulling in a chunk of code from NVGPU to fixup our
SMID mappings on Volta and above, which depends on ppc_nr[gpc]
reflecting the actual number of PPCs present, not the maximum number.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent 9aa3face

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c

+1 −1
Original line number Diff line number Diff line
@@ -257,7 +257,7 @@ gf117_grctx_generate_attrib(struct gf100_gr_chan *chan) 
	gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);



	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {

		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {

		for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) {

			const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];

			const u32 b =  beta * gr->ppc_tpc_nr[gpc][ppc];

			const u32 t = timeslice_mode;

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c

+1 −1
Original line number Diff line number Diff line
@@ -912,7 +912,7 @@ gm107_grctx_generate_attrib(struct gf100_gr_chan *chan) 
	gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);



	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {

		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {

		for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {

			const u32 as =  alpha * gr->ppc_tpc_nr[gpc][ppc];

			const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];

			const u32 u = 0x418ea0 + (n * 0x04);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c

+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ gm200_grctx_generate_dist_skip_table(struct gf100_gr *gr) 
	int gpc, ppc, i;



	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {

		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {

		for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) {

			u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc];

			u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc];

			while (ppc_tpcs-- > gr->ppc_tpc_min)

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c

+1 −1
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ gp100_grctx_generate_attrib(struct gf100_gr_chan *chan) 
	gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);



	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {

		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {

		for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {

			const u32 as =  alpha * gr->ppc_tpc_nr[gpc][ppc];

			const u32 bs = attrib * gr->ppc_tpc_max;

			const u32 u = 0x418ea0 + (n * 0x04);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c

+1 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ gp102_grctx_generate_attrib(struct gf100_gr_chan *chan) 
	gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);



	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {

		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {

		for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {

			const u32 as =  alpha * gr->ppc_tpc_nr[gpc][ppc];

			const u32 bs = attrib * gr->ppc_tpc_max;

			const u32 gs =   gfxp * gr->ppc_tpc_max;