Commit 0cc6f45c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull iommu updates from Joerg Roedel:
 "Core:
   - IOMMU memory usage observability - This will make the memory used
     for IO page tables explicitly visible.
   - Simplify arch_setup_dma_ops()

  Intel VT-d:
   - Consolidate domain cache invalidation
   - Remove private data from page fault message
   - Allocate DMAR fault interrupts locally
   - Cleanup and refactoring

  ARM-SMMUv2:
   - Support for fault debugging hardware on Qualcomm implementations
   - Re-land support for the ->domain_alloc_paging() callback

  ARM-SMMUv3:
   - Improve handling of MSI allocation failure
   - Drop support for the "disable_bypass" cmdline option
   - Major rework of the CD creation code, following on directly from
     the STE rework merged last time around.
   - Add unit tests for the new STE/CD manipulation logic

  AMD-Vi:
   - Final part of SVA changes with generic IO page fault handling

  Renesas IPMMU:
   - Add support for R8A779H0 hardware

  ... and a couple smaller fixes and updates across the sub-tree"

* tag 'iommu-updates-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (80 commits)
  iommu/arm-smmu-v3: Make the kunit into a module
  arm64: Properly clean up iommu-dma remnants
  iommu/amd: Enable Guest Translation after reading IOMMU feature register
  iommu/vt-d: Decouple igfx_off from graphic identity mapping
  iommu/amd: Fix compilation error
  iommu/arm-smmu-v3: Add unit tests for arm_smmu_write_entry
  iommu/arm-smmu-v3: Build the whole CD in arm_smmu_make_s1_cd()
  iommu/arm-smmu-v3: Move the CD generation for SVA into a function
  iommu/arm-smmu-v3: Allocate the CD table entry in advance
  iommu/arm-smmu-v3: Make arm_smmu_alloc_cd_ptr()
  iommu/arm-smmu-v3: Consolidate clearing a CD table entry
  iommu/arm-smmu-v3: Move the CD generation for S1 domains into a function
  iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry()
  iommu/arm-smmu-v3: Add an ops indirection to the STE code
  iommu/arm-smmu-qcom: Don't build debug features as a kernel module
  iommu/amd: Add SVA domain support
  iommu: Add ops->domain_alloc_sva()
  iommu/amd: Initial SVA support for AMD IOMMU
  iommu/amd: Add support for enable/disable IOPF
  iommu/amd: Add IO page fault notifier handler
  ...
parents f0cd69b8 2bd5059c

Documentation/admin-guide/cgroup-v2.rst

+1 −1
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@@ -1435,7 +1435,7 @@ PAGE_SIZE multiple when read back. 
	  sec_pagetables

		Amount of memory allocated for secondary page tables,

		this currently includes KVM mmu allocations on x86

		and arm64.

		and arm64 and IOMMU page tables.



	  percpu (npn)

		Amount of memory used for storing per-cpu kernel

Documentation/devicetree/bindings/iommu/qcom,tbu.yaml

0 → 100644
+69 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/iommu/qcom,tbu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm TBU (Translation Buffer Unit)



maintainers:

  - Georgi Djakov <quic_c_gdjako@quicinc.com>



description:

  The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains

  a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides

  debug features to trace and trigger debug transactions. There are multiple TBU

  instances with each client core.



properties:

  compatible:

    enum:

      - qcom,sc7280-tbu

      - qcom,sdm845-tbu



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  interconnects:

    maxItems: 1



  power-domains:

    maxItems: 1



  qcom,stream-id-range:

    description: |

      Phandle of a SMMU device and Stream ID range (address and size) that

      is assigned by the TBU

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: phandle of a smmu node

          - description: stream id base address

          - description: stream id size



required:

  - compatible

  - reg

  - qcom,stream-id-range



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sdm845.h>

    #include <dt-bindings/interconnect/qcom,icc.h>

    #include <dt-bindings/interconnect/qcom,sdm845.h>



    tbu@150e1000 {

        compatible = "qcom,sdm845-tbu";

        reg = <0x150e1000 0x1000>;

        clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;

        interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY

                         &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;

        power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;

        qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;

    };

...

Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml

+1 −0
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@@ -50,6 +50,7 @@ properties: 
              - renesas,ipmmu-r8a779a0           # R-Car V3U

              - renesas,ipmmu-r8a779f0           # R-Car S4-8

              - renesas,ipmmu-r8a779g0           # R-Car V4H

              - renesas,ipmmu-r8a779h0           # R-Car V4M

          - const: renesas,rcar-gen4-ipmmu-vmsa  # R-Car Gen4



  reg:

Documentation/filesystems/proc.rst

+2 −2
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@@ -1110,8 +1110,8 @@ KernelStack 
PageTables

              Memory consumed by userspace page tables

SecPageTables

              Memory consumed by secondary page tables, this currently

              currently includes KVM mmu allocations on x86 and arm64.

              Memory consumed by secondary page tables, this currently includes

              KVM mmu and IOMMU allocations on x86 and arm64.

NFS_Unstable

              Always zero. Previous counted pages which had been written to

              the server, but has not been committed to stable storage.

arch/arc/mm/dma.c

+1 −2
Original line number Diff line number Diff line
@@ -90,8 +90,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, 
/*

 * Plug in direct dma map ops.

 */

void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,

			bool coherent)

void arch_setup_dma_ops(struct device *dev, bool coherent)

{

	/*

	 * IOC hardware snoops all DMA traffic keeping the caches consistent