Unverified Commit 0d495db1 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Arnd Bergmann
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arm64: dts: cavium: thunder2: Add missing PL011 "uartclk" 



The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
Thunder2 SoC is missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.

Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250609215706.3009692-2-robh@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent f060fee2

arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -136,8 +136,8 @@ uart0: serial@402020000 { 
			reg = <0x04 0x02020000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk125mhz>;

			clock-names = "apb_pclk";

			clocks = <&clk125mhz>, <&clk125mhz>;

			clock-names = "uartclk", "apb_pclk";

		};

	};