Unverified Commit 0eb51277 authored by Charlie Jenkins's avatar Charlie Jenkins Committed by Palmer Dabbelt
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riscv: Fix default misaligned access trap 



Commit d1703dc7 ("RISC-V: Detect unaligned vector accesses
supported") removed the default handlers for handle_misaligned_load()
and handle_misaligned_store(). When the kernel is compiled without
RISCV_SCALAR_MISALIGNED, these handlers are never defined, causing
compilation errors.

Signed-off-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Fixes: d1703dc7 ("RISC-V: Detect unaligned vector accesses supported")
Reviewed-by: default avatarJesse Taube <mr.bossman075@gmail.com>
Link: https://lore.kernel.org/r/20241108-fix_handle_misaligned_load-v2-1-91d547ce64db@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 64f7b77f

arch/riscv/include/asm/entry-common.h

+12 −0
Original line number Diff line number Diff line
@@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, 
void handle_page_fault(struct pt_regs *regs);

void handle_break(struct pt_regs *regs);



#ifdef CONFIG_RISCV_MISALIGNED

int handle_misaligned_load(struct pt_regs *regs);

int handle_misaligned_store(struct pt_regs *regs);

#else

static inline int handle_misaligned_load(struct pt_regs *regs)

{

	return -1;

}



static inline int handle_misaligned_store(struct pt_regs *regs)

{

	return -1;

}

#endif



#endif /* _ASM_RISCV_ENTRY_COMMON_H */