Commit 11b72b1c authored by Ziyue Zhang's avatar Ziyue Zhang Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: hamoa: Fix incomplete Root Port property migration 



Historically, the Qualcomm PCIe controller node (Host bridge) described
all Root Port properties, such as PHY, PERST#, and WAKE#. But to provide
a more accurate hardware description and to support future multi-Root Port
controllers, these properties were moved to the Root Port node in the
devicetree bindings.

Commit 960609b2 ("arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake
GPIOs to PCIe port nodes and add port Nodes for all PCIe ports")
initiated this transition for the Hamoa platform by moving the PHY
property to the Root Port node in hamoa.dtsi. However, it only updated
some platform specific DTS files for PERST# and WAKE#, leaving others in
a "mixed" binding state.

While the PCIe controller driver supports both legacy and Root Port
bindings, It cannot correctly handle a mix of both. In these cases, the
driver parses the PHY from the Root Port node, but fails to find the
PERST# property (which it then assumes is not present, as it is optional).
Consequently, the controller probe succeeds, but PERST# remains
uncontrolled, preventing PCIe endpoints from functioning.

So, fix the incomplete migration by moving the PERST# and WAKE# properties
from the controller node to the Root Port node in all remaining Hamoa
platform DTS files.

Fixes: 960609b2 ("arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports")
Signed-off-by: default avatarZiyue Zhang <ziyue.zhang@oss.qualcomm.com>
Reviewed-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260330020934.3501247-1-ziyue.zhang@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 88bdac54

arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi

+10 −6
Original line number Diff line number Diff line
@@ -1032,9 +1032,6 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";
@@ -1048,10 +1045,12 @@ &pcie4_phy { 
	status = "okay";

};



&pcie6a {

	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

&pcie4_port0 {

	reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;

};



&pcie6a {

	vddpe-3v3-supply = <&vreg_nvme>;



	pinctrl-0 = <&pcie6a_default>;
@@ -1067,6 +1066,11 @@ &pcie6a_phy { 
	status = "okay";

};



&pcie6a_port0 {

	reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

};



&pm8550_gpios {

	rtmr0_default: rtmr0-reset-n-active-state {

		pins = "gpio10";

arch/arm64/boot/dts/qcom/x1-crd.dtsi

+15 −9
Original line number Diff line number Diff line
@@ -1216,15 +1216,17 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";



	status = "okay";

};



&pcie4_port0 {

	reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;

};



&pcie4_phy {

	vdda-phy-supply = <&vreg_l3i_0p8>;

	vdda-pll-supply = <&vreg_l3e_1p2>;
@@ -1233,9 +1235,6 @@ &pcie4_phy { 
};



&pcie5 {

	perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;



	vddpe-3v3-supply = <&vreg_wwan>;



	pinctrl-0 = <&pcie5_default>;
@@ -1251,10 +1250,12 @@ &pcie5_phy { 
	status = "okay";

};



&pcie6a {

	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

&pcie5_port0 {

	reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;

};



&pcie6a {

	vddpe-3v3-supply = <&vreg_nvme>;



	pinctrl-names = "default";
@@ -1270,6 +1271,11 @@ &pcie6a_phy { 
	status = "okay";

};



&pcie6a_port0 {

	reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

};



&pm8550_gpios {

	kypd_vol_up_n: kypd-vol-up-n-state {

		pins = "gpio6";

arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi

+8 −6
Original line number Diff line number Diff line
@@ -1081,9 +1081,6 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";
@@ -1098,6 +1095,9 @@ &pcie4_phy { 
};



&pcie4_port0 {

	reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	wifi@0 {

		compatible = "pci17cb,1107";

		reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1115,9 +1115,6 @@ wifi@0 { 
};



&pcie6a {

	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;



	vddpe-3v3-supply = <&vreg_nvme>;



	pinctrl-0 = <&pcie6a_default>;
@@ -1126,6 +1123,11 @@ &pcie6a { 
	status = "okay";

};



&pcie6a_port0 {

	reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

};



&pcie6a_phy {

	vdda-phy-supply = <&vreg_l1d_0p8>;

	vdda-pll-supply = <&vreg_l2j_1p2>;

arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi

+8 −6
Original line number Diff line number Diff line
@@ -1065,9 +1065,6 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";
@@ -1082,6 +1079,9 @@ &pcie4_phy { 
};



&pcie4_port0 {

	reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	wifi@0 {

		compatible = "pci17cb,1107";

		reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1099,9 +1099,6 @@ wifi@0 { 
};



&pcie6a {

	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;



	vddpe-3v3-supply = <&vreg_nvme>;



	pinctrl-0 = <&pcie6a_default>;
@@ -1110,6 +1107,11 @@ &pcie6a { 
	status = "okay";

};



&pcie6a_port0 {

	reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

};



&pcie6a_phy {

	vdda-phy-supply = <&vreg_l1d_0p8>;

	vdda-pll-supply = <&vreg_l2j_1p2>;

arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi

+5 −3
Original line number Diff line number Diff line
@@ -964,9 +964,6 @@ wifi@0 { 
};



&pcie6a {

	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;



	vddpe-3v3-supply = <&vreg_nvme>;



	pinctrl-0 = <&pcie6a_default>;
@@ -982,6 +979,11 @@ &pcie6a_phy { 
	status = "okay";

};



&pcie6a_port0 {

	reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

};



&pm8550_gpios {

	rtmr0_default: rtmr0-reset-n-active-state {

		pins = "gpio10";