Unverified Commit 1803012a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-microchip-6.18-2' of... 

Merge tag 'clk-microchip-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip

Pull Microchip clk driver updates from Nicolas Ferre:

 - add one clock for sam9x75
 - new meaning for MCR register field in clk-master
 - use force-write to PLL update register to ensure
   reliable programming sequence
 - update Analog Control Register (ACR) management to accommodate
   differences across SoCs.
 - ACR management dependency with one ARM PM patch added beforehand

* tag 'clk-microchip-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: at91: remove default values for PMC_PLL_ACR
  clk: at91: add ACR in all PLL settings
  clk: at91: sam9x7: Add peripheral clock id for pmecc
  clk: at91: clk-master: Add check for divide by 3
  clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register
  ARM: at91: pm: save and restore ACR during PLL disable/enable
parents 8f5ae30d 652b08af

arch/arm/mach-at91/pm_suspend.S

+7 −1
Original line number Diff line number Diff line
@@ -689,6 +689,10 @@ sr_dis_exit: 
	bic	tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID

	str	tmp2, [pmc, #AT91_PMC_PLL_UPDT]



	/* save acr */

	ldr	tmp2, [pmc, #AT91_PMC_PLL_ACR]

	str	tmp2, .saved_acr



	/* save div. */

	mov	tmp1, #0

	ldr	tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
@@ -758,7 +762,7 @@ sr_dis_exit: 
	str	tmp1, [pmc, #AT91_PMC_PLL_UPDT]



	/* step 2. */

	ldr	tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA

	ldr	tmp1, .saved_acr

	str	tmp1, [pmc, #AT91_PMC_PLL_ACR]



	/* step 3. */
@@ -1207,6 +1211,8 @@ ENDPROC(at91_pm_suspend_in_sram) 
#endif

.saved_mckr:

	.word 0

.saved_acr:

	.word 0

.saved_pllar:

	.word 0

.saved_sam9_lpr:

drivers/clk/at91/clk-master.c

+3 −0
Original line number Diff line number Diff line
@@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw, 
{

	struct clk_master *master = to_clk_master(hw);



	if (master->div == MASTER_PRES_MAX)

		return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);



	return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));

}

drivers/clk/at91/clk-sam9x60-pll.c

+41 −41
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) 


	spin_lock_irqsave(core->lock, flags);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_ID_MSK, core->id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);

	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
@@ -103,11 +103,8 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) 
	    (cmul == frac->mul && cfrac == frac->frac))

		goto unlock;



	/* Recommended value for PMC_PLL_ACR */

	if (core->characteristics->upll)

		val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;

	else

		val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;

	/* Load recommended value for PMC_PLL_ACR */

	val = core->characteristics->acr;

	regmap_write(regmap, AT91_PMC_PLL_ACR, val);



	regmap_write(regmap, AT91_PMC_PLL_CTRL1,
@@ -128,7 +125,7 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) 
		udelay(10);

	}



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -136,7 +133,7 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) 
			   AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,

			   AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -164,7 +161,7 @@ static void sam9x60_frac_pll_unprepare(struct clk_hw *hw) 


	spin_lock_irqsave(core->lock, flags);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_ID_MSK, core->id);



	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
@@ -173,7 +170,7 @@ static void sam9x60_frac_pll_unprepare(struct clk_hw *hw) 
		regmap_update_bits(regmap, AT91_PMC_PLL_ACR,

				   AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -262,7 +259,7 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, 


	spin_lock_irqsave(core->lock, irqflags);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

			  core->id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);

	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
@@ -275,7 +272,7 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, 
		     (frac->mul << core->layout->mul_shift) |

		     (frac->frac << core->layout->frac_shift));



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -284,7 +281,7 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, 
			   AT91_PMC_PLL_CTRL0_ENLOCK |

			   AT91_PMC_PLL_CTRL0_ENPLL);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -338,7 +335,10 @@ static const struct clk_ops sam9x60_frac_pll_ops_chg = { 
	.restore_context = sam9x60_frac_pll_restore_context,

};



/* This function should be called with spinlock acquired. */

/* This function should be called with spinlock acquired.

 * Warning: this function must be called only if the same PLL ID was set in

 *          PLL_UPDT register previously.

 */

static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,

				    bool enable)

{
@@ -350,7 +350,7 @@ static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, 
			   core->layout->div_mask | ena_msk,

			   (div << core->layout->div_shift) | ena_val);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -366,7 +366,7 @@ static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) 
	unsigned int val, cdiv;



	spin_lock_irqsave(core->lock, flags);

	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_ID_MSK, core->id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);

	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
@@ -398,13 +398,13 @@ static void sam9x60_div_pll_unprepare(struct clk_hw *hw) 


	spin_lock_irqsave(core->lock, flags);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_ID_MSK, core->id);



	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,

			   core->layout->endiv_mask, 0);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -518,7 +518,7 @@ static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, 
	div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;



	spin_lock_irqsave(core->lock, irqflags);

	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

			  core->id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);

	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
@@ -574,7 +574,7 @@ static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier, 
	div->div = div->safe_div;



	spin_lock_irqsave(core.lock, irqflags);

	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

			  core.id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);

	cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;

drivers/clk/at91/pmc.h

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ struct clk_pll_characteristics { 
	u16 *icpll;

	u8 *out;

	u8 upll : 1;

	u32 acr;

};



struct clk_programmable_layout {

drivers/clk/at91/sam9x60.c

+2 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ static const struct clk_pll_characteristics plla_characteristics = { 
	.num_output = ARRAY_SIZE(plla_outputs),

	.output = plla_outputs,

	.core_output = core_outputs,

	.acr = UL(0x00020010),

};



static const struct clk_range upll_outputs[] = {
@@ -48,6 +49,7 @@ static const struct clk_pll_characteristics upll_characteristics = { 
	.output = upll_outputs,

	.core_output = core_outputs,

	.upll = true,

	.acr = UL(0x12023010), /* fIN = [18 MHz, 32 MHz]*/

};



static const struct clk_pll_layout pll_frac_layout = {