Commit 190b7415 authored by Atish Patra's avatar Atish Patra Committed by Anup Patel
Browse files

RISC-V: KVM: Add support for Raw event v2 



SBI v3.0 introduced a new raw event type v2 for wider mhpmeventX
programming. Add the support in kvm for that.

Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Signed-off-by: default avatarAtish Patra <atishp@rivosinc.com>
Acked-by: default avatarPaul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-3-d8f80cacb884@rivosinc.com


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 656ef2ea

arch/riscv/kvm/vcpu_pmu.c

+4 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ static u32 kvm_pmu_get_perf_event_type(unsigned long eidx) 
		type = PERF_TYPE_HW_CACHE;

		break;

	case SBI_PMU_EVENT_TYPE_RAW:

	case SBI_PMU_EVENT_TYPE_RAW_V2:

	case SBI_PMU_EVENT_TYPE_FW:

		type = PERF_TYPE_RAW;

		break;
@@ -128,6 +129,9 @@ static u64 kvm_pmu_get_perf_event_config(unsigned long eidx, uint64_t evt_data) 
	case SBI_PMU_EVENT_TYPE_RAW:

		config = evt_data & RISCV_PMU_RAW_EVENT_MASK;

		break;

	case SBI_PMU_EVENT_TYPE_RAW_V2:

		config = evt_data & RISCV_PMU_RAW_EVENT_V2_MASK;

		break;

	case SBI_PMU_EVENT_TYPE_FW:

		if (ecode < SBI_PMU_FW_MAX)

			config = (1ULL << 63) | ecode;